Staff Design Verification Engineer - High Performance CPU Core

Job Title

Staff Design Verification Engineer - High Performance CPU Core

Role Summary

Senior individual-contributor in the CPU Design Verification organization responsible for verification strategy, planning, and execution for high-performance out-of-order CPU core blocks and core-level interactions.

You will collaborate with architecture, RTL, performance, and verification teams to identify risks early, define effective verification approaches, and ensure high-quality signoff for complex CPU features.

Experience Level

Senior — 7+ years of relevant experience in ASIC, CPU/core, or SoC design verification.

Responsibilities

Primary responsibilities focus on verification strategy, execution, and improving verification quality across high-performance core features.

• Own verification planning and execution for one or more high-performance CPU core areas (e.g., Frontend, Midcore, Load-Store Unit, Hardware Prefetch).
• Drive block- and core-level verification: debug, coverage analysis, and closure for complex microarchitectural behavior.
• Define verification strategies for instruction fetch, branch prediction, issue/dispatch, pipeline interactions, load/store ordering, memory consistency, and prefetch correctness.
• Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models.
• Partner with architecture and design teams early to review specifications, remove ambiguity, and improve debugability.
• Lead failure analysis and root-cause debug across specification, RTL, tests, and infrastructure.
• Contribute reusable methodology, infrastructure, and technical guidance to improve verification productivity and quality across core generations.

Requirements

Key must-have skills and experience; followed by desirable skills.

Must-have:

• 7+ years of relevant ASIC, CPU/core, or SoC design verification experience.
• Hands-on SystemVerilog and UVM verification experience.
• Direct CPU/core verification experience with solid understanding of computer architecture and microarchitecture.
• Experience in high-performance CPU areas such as Frontend, Midcore, Load-Store Unit, memory ordering/consistency, or hardware prefetch.
• Strong verification flow knowledge: test planning, constrained-random or directed stimulus, failure analysis, coverage analysis, and coverage closure.
• Strong debug skills and ability to translate architectural intent into verification strategy and execution.

Nice-to-have:

• Experience with out-of-order core verification.
• Experience using formal verification and/or emulation for high-risk or performance-sensitive problems.
• Experience collaborating with performance, compiler, system verification, and software teams.
• Experience mentoring engineers and influencing verification methodology across teams.
• Familiarity with Python, C/C++, or other scripting/programming languages for DV infrastructure and automation.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (BS/MS). The posting specifies degree-level requirements; equivalent practical experience is not listed.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.