UVM Digital Verification Engineer

Job Title

UVM Digital Verification Engineer

Role Summary

Join Draper's Digital Design Team to develop and execute verification strategies for FPGA and ASIC designs across embedded security, cryptography, signal/image processing, navigation, and communications domains. Work with cross-disciplinary teams to verify complex digital and mixed-signal systems and drive designs to meet performance, power, and functional requirements.

Experience Level

Mid-level. Typical experience: 3–5 years with a bachelor's degree, or 0–2 years with a master's degree in relevant fields.

Responsibilities

Develop and execute verification approaches and collaborate with RTL designers to close coverage and functional issues.

• Author and execute verification plans and testbenches using UVM/UVMF.
• Develop UVM agents and instantiate VIP for industry-standard buses.
• Create and run block- and chip-level UVM test environments; perform constrained-random testing and coverage-driven verification.
• Implement cover groups and drive code/functional coverage to closure.
• Use formal analysis tools to augment verification where applicable.
• Perform simulation, debug, and resolution of RTL/simulation issues with design teams.
• Participate in code reviews and mentor junior engineers.
• Contribute to system-level design reviews, hardware feasibility assessments, and optimization for performance, power, and cost.
• Perform or guide physical layout activities (floor-planning, extracted-parasitic simulation) when required.

Requirements

Core technical skills and clearances needed to perform the role.

• Must-have: Proficiency in SystemVerilog (including SVA) and recent hands-on experience with UVM/UVMF.
• Must-have: Experience with at least one major simulator (QuestaSim, Xcelium, VCS).
• Must-have: Practical knowledge of constrained-random testing, coverage-driven verification, and implementing cover groups.
• Must-have: Experience with common bus protocols and VIP (examples: DDR3/DDR4, AMBA AXI).
• Must-have: Familiarity with formal analysis tools and scripting (Python, Perl, Bash) for verification automation.
• Must-have: Comfortable working in a Linux environment and strong debugging/analysis skills.
• Must-have: Ability to obtain and maintain a U.S. government security clearance.
• Nice-to-have: Background in transistor-level simulation, floor-planning, or mixed-signal verification.
• Nice-to-have: Experience mentoring junior engineers and participating in system-architecture trade studies.

Education Requirements

Requires a Bachelor’s degree in Engineering or a related field. Master’s degree preferred. Relevant fields listed include Integrated Circuits, ASIC Hardware Engineering, Electrical Engineering, Computer Engineering, Computer Science, or other related technical disciplines.

About the Company

Company: Draper

Headquarters: Cambridge, MA, United States

Draper is an independent, nonprofit research and development organization based in Cambridge, Massachusetts. With over 2,000 employees, Draper develops advanced technologies in defense, space, biomedical engineering, and other national-security and commercial domains through multidisciplinary teams of engineers and scientists.