UVM Digital Verification Engineer

Job Title

UVM Digital Verification Engineer

Role Summary

Join Draper's Digital Design Team to develop and execute verification strategies for complex FPGA and ASIC digital and mixed-signal designs in embedded security, cryptography, signal/image processing, navigation, and communications.

The role focuses on UVM-based verification, formal analysis, and collaboration with RTL designers to close functional and code coverage across block- and chip-level testbenches.

Experience Level

Mid-level. Typical guidance: 3–5 years' relevant experience with a bachelor's degree, or 0–2 years with a master's degree.

Responsibilities

Primary responsibilities include planning, implementing, and executing verification for digital designs.

• Develop verification strategies and write verification plans.
• Author UVM agents and build block- and chip-level UVM testbenches.
• Instantiate and integrate VIP for industry-standard buses.
• Implement constrained-random tests, covergroups, and drive coverage closure (code & functional).
• Apply formal analysis tools to verify properties and support verification closure.
• Work with RTL designers to debug and resolve simulation issues.
• Perform code reviews and mentor junior engineers.
• Automate verification flows using scripting and run simulations on industry simulators.

Requirements

Must-have skills, tools, and clearances.

• Fluent in SystemVerilog, including SVA.
• Recent, hands-on experience with UVM/UVMF.
• Familiarity with at least one major industry simulator (QuestaSim, Xcelium, VCS).
• Experience with common bus protocols (examples: DDR3/DDR4, AMBA AXI).
• Strong grasp of constrained-random testing and coverage-driven verification.
• Experience using formal analysis tools/methodology.
• Practical scripting skills (Python, Perl, Bash, or similar) and ability to work in Linux.
• Strong analytical, communication, and problem-solving skills; attention to detail and time management.
• Ability to obtain and maintain a U.S. government security clearance (required for selected applicants).

Education Requirements

Requires a bachelor's degree in Engineering or a related field; a master's degree is preferred. The posting links experience to degree level: 3–5 years' experience with a bachelor's degree, or 0–2 years' experience with a master's degree. Fields mentioned include Integrated Circuits, ASIC Hardware Engineering, or related technical disciplines. No specific certifications were listed; equivalent practical experience is acceptable per the experience-based guidance above.

About the Company

Company: Draper

Headquarters: Cambridge, MA, United States

Draper is an independent, nonprofit research and development organization based in Cambridge, Massachusetts. With over 2,000 employees, Draper develops advanced technologies in defense, space, biomedical engineering, and other national-security and commercial domains through multidisciplinary teams of engineers and scientists.