TPM Lead

Job Title

TPM Lead

Role Summary

Technical Program Manager leading schedule, risk management, and cross-team coordination for end-to-end silicon development. Partner with engineering leads and executives to translate company objectives into actionable milestones and ensure on-time delivery.

The role coordinates distributed engineering teams across Mountain View and other international offices and provides concise technical status and risk reporting for leadership.

Experience Level

Senior. Requires extensive semiconductor program experience; posting requests 10+ years in semiconductor development and 3+ years as a TPM or program lead on complex ASIC/SoC projects.

Responsibilities

Own program schedule, surface status to leadership, and remove delivery blockers across the silicon lifecycle.

• Break down company objectives into milestones and drive execution across the engineering organization.
• Own and maintain the schedule across architecture, RTL, verification, synthesis, physical design, tapeout, packaging, post-silicon bring-up and validation.
• Coordinate multi-site efforts (Mountain View, New York, London, Zurich, Copenhagen) and manage dependencies between teams.
• Define metrics and build dashboards to track progress and surface critical information.
• Identify, communicate, and mitigate risks to schedule and quality; escalate when needed.
• Synthesize technical status, trade-offs, and risks into clear updates for executive leadership.

Requirements

Must-have skills and experience needed to perform the role.

• 10+ years in semiconductor development, including 3+ years as a TPM or program lead on complex ASIC/SoC architectures.
• Proven experience across the full silicon lifecycle: architecture, RTL generation, verification, tapeout, bring-up and post-silicon validation.
• Experience with complex software/hardware integration projects.
• Strong communication and stakeholder management; ability to influence without authority.
• Proven track record managing internationally distributed engineering teams.
• Proficiency with program management tools such as Jira, Asana, or Linear.
• Problem-solving mindset and ability to find practical solutions under schedule pressure.

Nice-to-have:

• Familiarity with chiplets, 3D packaging, heterogeneous AI inference systems, or experience with external foundries/OSAT vendors.
• Experience at a silicon startup and advanced use of Linear for program tracking.

Education Requirements

Preferred: Ph.D. in an electrical engineering discipline (listed as a bonus). No specific required degree or field-of-study was stated as mandatory in the posting.

About the Company

Company: Normal Computing

Headquarters: New York, NY, USA

Normal Computing develops software and hardware solutions for the semiconductor and AI infrastructure industries, specializing in ASICs for image and video diffusion inference and AI accelerators. The company focuses on architecture and microarchitecture of compute blocks, PE array design, ISA co-design, and FPGA prototyping.