Timing Engineer

Job Title

Timing Engineer

Role Summary

The Timing Engineer leads timing activities for a subsystem within the Physical Design organization, partnering with Design, Architecture, and Physical Design teams to achieve timing convergence from implementation through sign-off.

Work focuses on static timing analysis, timing constraints, timing-closure methodologies, and automation for advanced semiconductor process nodes.

Experience Level

Mid-level — requires 5+ years of relevant ASIC or FPGA timing analysis and sign-off experience.

Responsibilities

Primary responsibilities include technical leadership of timing closure and delivery of sign-off quality timing results for block and subsystem designs.

• Drive timing closure at block and subsystem levels and coordinate with full-chip teams for convergence.
• Develop timing methodologies, flows, and scripts to improve interface timing closure at full-chip scale.
• Define and manage I/O and hierarchical timing budgets across designs.
• Apply advanced sign-off methodologies (including POCV, OCV, and PVT effects) for advanced nodes.
• Manage large-scale multi-corner/multi-mode (MCMM) STA runs with automation and partitioning for efficient resource use.
• Provide actionable timing feedback, root-cause analysis, and ECO guidance to RTL and physical design teams.
• Generate and validate timing ECOs and support rapid implementation cycles.
• Lead global clock planning and clock-architecture optimization to simplify interface timing closure.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Must-have: 5+ years of experience in timing analysis, static timing analysis (STA), and timing sign-off at both block and full-chip levels.
• Must-have: Experience with synthesis, place-and-route, and parasitic extraction flows.
• Must-have: Experience performing multi-corner, multi-mode (MCMM) timing analysis and applying OCV/POCV/PVT sign-off methods.
• Must-have: Proficiency with industry timing tools such as Cadence Tempus and Synopsys PrimeTime.
• Must-have: Experience developing automation and scripting using Tcl, Python, and/or Perl.
• Must-have: Demonstrated ability to collaborate with RTL Design, Architecture, Physical Design, and full-chip teams and to work independently with strong prioritization and problem-solving skills.
• Nice-to-have: Experience with advanced FPGA or high-performance ASIC designs and hierarchical timing methodologies for large designs.
• Nice-to-have: Familiarity with clock tree synthesis (CTS), clock planning, and clock-architecture optimization.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field and 5+ years of experience in ASIC or FPGA timing analysis and sign-off.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.