Power Management Design Engineer

Job Title

Power Management Design Engineer

Role Summary

This role designs power-management, reset, and clocking solutions for high-performance RISC-V CPU and SoC IP. The engineer will work with architecture, verification, physical implementation, and software teams to deliver configurable hardware IP with strong attention to performance, area, and power.

Experience Level

Mid-level. The posting requests 3+ years of relevant industry experience in CPU and SoC clocking, reset, and power-management logic design.

Responsibilities

Primary responsibilities include micro-architecture, RTL design, verification coordination, and cross-functional implementation work.

• Define power-management requirements with the architecture team.
• Architect, design, and implement clocking, reset, and power-management logic and control.
• Produce microarchitecture specifications and documentation; share design knowledge with the team.
• Perform initial sandbox verification and collaborate with design verification to create and execute test plans.
• Work with physical implementation teams to meet frequency, area, and power targets.
• Collaborate with software teams to enable and optimize power-management features.

Requirements

Must-have technical skills and experience:

• 3+ years of industry experience in CPU and SoC clocking, reset, and power-management logic designs.
• Experience with high-performance, energy-efficient CPU and SoC design and delivery from architecture through tapeout.
• Expertise in reset control and clocking strategies: clock distribution, dynamic clocking, clock gating, and clock boundary crossing.
• Power-management experience: power state definition/management, PMU design, retention and power sequencing, DVFS, and Di/dt mitigation.
• Understanding of DFT, MBIST, debug and error handling, and power-aware simulation.
• Proficiency in RTL design using Verilog, SystemVerilog, or VHDL.
• Familiarity with RTL quality checks (lint, CDC, RDC); hands-on Spyglass experience is a plus.
• Knowledge of at least one object-oriented and/or functional programming language.
• Attention to detail and ability to work collaboratively in engineering teams.

Nice to have:

• Experience with AMBA protocols (AXI, AHB, APB) and AMBA Low Power interfaces (P-channel, Q-channel).
• Experience with Scala/Chisel, Bluespec, or other hardware DSLs for configurable hardware generators.
• Knowledge of RISC-V architecture.
• Experience with Git/GitHub, Jira, and Confluence.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline, or equivalent practical experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.