Job Title
Test Engineering Director
Role Summary
The Test Engineering Director leads test strategy, development, and deployment for Marvell silicon products, with a focus on IO chiplet-based, high-speed and high-power devices for AI and advanced compute. This role manages cross-functional teams, vendor relationships, and production test flows to ensure product quality and scalable manufacturing.
Experience Level
Senior — expects extensive industry experience; the posting specifies 12+ years in semiconductor test engineering with 6+ years leading engineering teams.
Responsibilities
Accountable for end-to-end test engineering strategy, delivery, and continuous improvement across product life cycles and manufacturing.
- Define and lead test engineering strategy for IO chiplet-based products, including ATE platform selection and outsourced manufacturing test strategy.
- Establish and manage strategic partnerships with ATE vendors, OSATs, probe card suppliers, and instrumentation providers.
- Lead cross-functional engineering teams (design, package, product, systems, manufacturing, reliability) to develop test infrastructure and production flows.
- Build and manage teams for customer sample validation, silicon characterization, correlation, qualification, yield improvement, and high-volume test deployment.
- Architect scalable, reusable ATE IP, software frameworks, and automation methodologies across product families and packaging architectures.
- Own ATE hardware architecture, load board and socket strategy, probe card approach, and system verification to ensure signal, power, and thermal integrity.
- Drive initiatives to reduce test cost, improve throughput, shorten test time, and improve yield through DFT/DFM and manufacturing process improvements.
- Define data-driven yield analytics, failure analysis, correlation, and production monitoring across wafer sort, final test, and system-level test.
- Maintain complete documentation of test hardware, software, validation methods, and manufacturing procedures in configuration-managed systems.
Requirements
Must-have qualifications and experience required to perform the role effectively, followed by desirable skills.
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Must-have: Extensive technical leadership in high-speed/high-power semiconductor test development for AI, networking, or advanced compute applications.
- 12+ years of semiconductor test engineering experience, including 6+ years leading teams responsible for NPI, ATE development, characterization, correlation, and high-volume manufacturing.
- Proven record leading cross-functional organizations to deliver scalable ATE solutions and production test strategies.
- Strong experience defining ATE architecture and reusable ATE IP platforms adaptable across chiplet-based MCM, CPC, and CPO products.
- Demonstrated experience in CAPEX/OPEX planning, resource forecasting, organizational scaling, and technology roadmap definition.
- Experience driving end-to-end wafer sort, package test, and system-level test strategies for advanced heterogeneous integration products.
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Nice-to-have: Hands-on experience with Advantest 93K or Teradyne UltraFLEX; deep knowledge of high-speed IO protocols, probe hardware, load board and socket design; software development for production in Python/C/C++; measurement methodologies up to 100GHz; experience with MCM, CPC, CPO, and 2.5D/3D integration.
Education Requirements
Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, Optical Engineering, Computer Science, or related disciplines. Formal certification or advanced training in ATE software architecture, automation frameworks, or semiconductor test methodologies is highly desired.
About the Company
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.

Date Posted: 2026-06-18