Test Engineer

Job Title

Test Engineer

Role Summary

Join Efficient Computer's Operations team as the primary test engineering interface across foundry, OSAT, and test partners. You will own test engineering for multiple chip programs, from DFT strategy and ATPG pattern delivery through ATE bring-up and production test.

This is a hands-on role at the intersection of Hardware Engineering and Supply Chain Operations focused on tapeout bring-up, test program development, and scaling test infrastructure for future products.

Experience Level

Mid-level (5+ years semiconductor test engineering experience)

Responsibilities

Lead and execute test engineering activities across tapeout, bring-up, and production for multiple chip programs.

• Define and execute DFT strategy; generate and validate ATPG patterns (scan, MBIST, JTAG) and setup sequences.
• Produce and maintain STIL and PDL test files for ATE execution and resolve pattern-level issues.
• Develop and debug ATE test programs (Advantest, Teradyne) and execute first-silicon bring-up with OSAT partners.
• Characterize device behavior across voltage, temperature, and frequency corners; support load-board bring-up.
• Define and manage test flows: wafer probe, final test, bin sort, die traceability, and OTP programming.
• Coordinate test program handoff, qualification, and pattern delivery with external OSAT and design partners.
• Track and analyze yield data, escalate anomalies, and drive corrective actions and test escapes.
• Build scalable test infrastructure, documentation, and processes that apply across programs.

Requirements

Must-have technical skills and practical experience for immediate contribution.

• 5+ years semiconductor test engineering experience in a fabless or IDM environment.
• Hands-on DFT experience: scan insertion, ATPG, MBIST, JTAG boundary scan.
• Experience generating and validating STIL patterns and managing test pattern delivery packages.
• ATE test program development experience on Advantest or Teradyne platforms.
• Experience supporting wafer probe and final test at an OSAT or test house, including load-board bring-up.
• Familiarity with power sequencing requirements and DFT entry flows for safe ATE bring-up.
• Ability to coordinate directly with external design partners, OSATs, and cross-functional internal teams; strong written and verbal communication skills.

Nice-to-have:

• Embedded memory test and characterization; non-volatile memory programming experience.
• High-speed serial interface test experience (memory, camera/display interconnects).
• Experience with DFT tools from major EDA vendors; exposure to leading-edge nodes (28nm and below).
• ATE yield analysis and test time optimization experience; scripting in Python or Perl for automation.
• Experience generating VCD from RTL simulation and converting to STIL.

Education Requirements

Not specified.

About the Company

Company: Efficient Computer

Headquarters: Austin, TX, USA

Developer of ultra-low-power general-purpose processors using patented technology that can consume up to 100x less energy than comparable ultra-low-power processors. Their programmable platform supports standard high-level languages and AI/ML frameworks to enable long-lived, battery-powered edge devices and energy-efficient SoCs for IoT and edge AI applications.