Technical Staff Engineer - Verification

Job Title

Technical Staff Engineer - Verification

Role Summary

Technical leader responsible for verification strategy and execution for next-generation Ethernet Switch and PCIe Switch SoCs. The role covers IP, subsystem, and full-SoC verification including CPU subsystems and AMBA interconnects using SystemVerilog UVM.

Drive scalable verification architecture, coverage-driven methodologies, protocol compliance, system-level debug, and mentor engineers to achieve first-silicon success.

Experience Level

Senior - typically 12+ years of ASIC/SoC verification experience with increasing technical leadership responsibilities.

Responsibilities

Primary responsibilities include technical leadership, verification architecture, and cross-team collaboration to deliver verified SoC products.

• Provide technical leadership for verification of complex Ethernet and PCIe Switch SoCs, covering datapath, control-plane, management, and CPU subsystems.
• Define and drive verification architecture, methodologies, and best practices across projects and teams.
• Lead verification of ARM/MIPS CPU subsystems and AMBA interconnects (AXI, AXI-Lite, AHB, APB).
• Architect scalable, reusable SystemVerilog UVM environments, agents, scoreboards, protocol checkers, and coverage frameworks.
• Plan and execute verification for PCIe (link training/LTSSM, enumeration, config space, error handling, NTB/hot-plug) and AMBA protocol corner-cases.
• Validate CPU subsystem behaviours: boot/reset, register access and RAL integration, DMA/memory interactions, interrupts and timers.
• Develop constrained-random, directed, and scenario-based strategies for realistic traffic and system workloads.
• Drive functional, code, assertion, and cross-coverage closure using metrics-driven approaches.
• Debug complex system-level issues spanning RTL, firmware interactions, interconnect fabrics, protocol layers, and UVM infrastructure.
• Collaborate with architecture, RTL, firmware, validation, emulation, and physical design teams; mentor verification engineers.

Requirements

Must-have technical skills and experience for the role; preferred items are listed separately.

• Typically 12+ years of ASIC/SoC verification experience with technical leadership responsibilities.
• Expert-level proficiency in SystemVerilog and UVM (advanced UVM architecture, reusable components, scoreboards, functional coverage, sequence layering, UVM RAL).
• Strong expertise in verifying AMBA interconnects (AXI, AXI-Lite, AHB, APB).
• Proven experience verifying Ethernet and/or PCIe-based SoCs and familiarity with PCIe protocol details.
• Strong understanding of ARM and/or MIPS CPU architectures and subsystem integration.
• Extensive experience with industry-standard simulators and debug tools (VCS, Questa, Xcelium).
• Strong scripting and automation skills (Python, Perl, Tcl, or equivalent).
• Excellent analytical, debugging, communication, and technical leadership skills; prior mentoring experience.
• Willingness/ability to travel up to 25%.

Nice-to-have

• Experience with SoC-level verification closure and multi-IP subsystem integration.
• Experience integrating firmware/software-driven verification flows.
• Exposure to AI/ML-based verification tools for intelligent debug, coverage optimization, failure classification, or test generation.
• Experience building metrics-driven verification environments and driving methodology standardization.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering or a related technical field.

About the Company

Company: Microchip

Headquarters: Chandler, Arizona, USA

Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.