Technical Staff Engineer - Design
MicrochipJob Title
Technical Staff Engineer - Design
Role Summary
Senior design engineer responsible for IO, pad ring, and bump pattern planning for advanced SoC storage and memory controller products in the Data Center Solutions business unit.
Work across architecture, implementation, packaging, verification, and foundry teams to take designs from concept through production and silicon validation.
Experience Level
Senior — 12+ years of related experience is expected.
Responsibilities
Primary responsibilities include planning and implementing IO/pad ring solutions and delivering handoff data for physical implementation.
- Own pad ring and bump pattern planning to meet package and system-level constraints.
- Develop and maintain IO connectivity, pad ring definitions, and bump maps throughout the design cycle.
- Produce and validate handoff deliverables (pad ring DEF, Verilog/IO netlists, bump maps) for downstream teams.
- Ensure IO and pad ring designs comply with design standards, packaging constraints, and implementation best practices.
- Collaborate with Architecture, IP Packaging, Implementation, Product Engineering, Technology Development, and Foundry teams to resolve IO/package issues.
- Support verification, emulation, ASIC validation, and silicon debug by analyzing IO-related issues and driving design improvements.
Requirements
Must-have technical skills and experience.
- Hands-on experience with pad ring planning, IO cell placement, and bump map/pattern definition for advanced SoC designs.
- Knowledge of IO library cells, IO standards, and PHY-level IO interfaces such as SerDes, DDR, PCIe, and CXL.
- Experience with IO planning and implementation EDA tools (e.g., Orbit IO, ISP, or equivalent).
- Experience generating and validating IO connectivity deliverables for physical design hand-off (DEF, IO netlist, bump assignment).
- Understanding of foundation and hard IP views including RTL, LEF, and Liberty files.
- Proficiency in flow automation and scripting using TCL and/or Python.
- Strong analytical skills, technical writing, and verbal communication.
- Preferred: familiarity with DFT (JTAG/Boundary Scan), RTL compilation/synthesis and Verilog/SystemVerilog, and project/versioning tools (SVN, JIRA).
Education Requirements
B.S. in Electrical Engineering required. M.S. in Electrical Engineering is preferred. (The role also expects approximately 12+ years of related engineering experience.)
About the Company
Company: Microchip
Headquarters: Chandler, Arizona, USA
Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.
