Technical Staff Engineer - CAD

Job Title

Technical Staff Engineer - CAD

Role Summary

Senior CAD engineer responsible for configuring, maintaining, and troubleshooting full‑custom and analog/mixed‑signal EDA flows for next‑generation Microchip FPGA/SOC products. The role supports internal design teams, interfaces with external tool vendors and foundries, and contributes tooling and automation that enable reliable tape‑outs.

Experience Level

Senior — 12+ years of relevant CAD/EDA engineering experience.

Responsibilities

Provide technical ownership of CAD environments and support analog/custom design teams and tape‑out activities.

• Install, configure, and maintain Cadence full‑custom environments (Virtuoso and Virtuoso Studio) and PDK/standard‑cell libraries.
• Support and troubleshoot physical verification flows (DRC/LVS) using Mentor Calibre and related runsets.
• Develop, test, and release automation scripts and tools (SKILL/Perl/Python) to improve analog/custom design productivity.
• Debug EDA tool issues impacting AMS/custom design, layout-to‑netlist flows (CDL, hspiceD, Verilog), and Cadence VXL problems.
• Manage LSF/DesignSync infrastructure and resolve related environment issues.
• Coordinate with engineering, operations, and external vendors/foundries to resolve tool/flow issues and support tape‑out readiness.
• Participate in tape‑out and foundry interface activities; verify design migration and Pcell workflows.
• Apply AI tools and automation techniques to accelerate deliverables where appropriate.

Requirements

Core technical skills and hands‑on experience required to perform the role.

• Must-have: In‑depth experience setting up and maintaining Cadence Virtuoso environments (Virtuoso 12, Virtuoso Studio IC 23.1+).
• Must-have: Experience with Pcell creation, debugging, and migration flows; handling standard cell libraries and PDK installations.
• Must-have: Strong scripting skills (SKILL, Perl, Python) for design automation and tool integration.
• Must-have: Experience writing and running DRC/LVS runsets (Mentor Calibre) and debugging physical verification issues.
• Must-have: Practical experience with CDL, hspiceD, Verilog netlisting customizations and AMS/custom EDA debugging.
• Must-have: Knowledge of Cadence VXL and ability to assist layout engineers with VXL issues; familiarity with LSF/DesignSync.
• Nice-to-have: Familiarity with 12nm and smaller process technologies including FinFET and prior foundry/tape‑out experience.
• Nice-to-have: Prior vendor interfacing experience and exposure to using AI tools to accelerate engineering tasks.
• Good written and verbal communication skills to coordinate across multiple sites/time zones.
• Travel requirement: 0%–25%.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering (BSEE or MSEE) specified in the posting.

About the Company

Company: Microchip

Headquarters: Chandler, Arizona, USA

Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.