Technical Program Manager, Silicon Physical Design

Job Title

Technical Program Manager, Silicon Physical Design

Role Summary

The Technical Program Manager will lead cross-functional execution for advanced SoC programs from planning through tapeout, coordinating physical design (PD), verification, validation, and bring-up across multiple teams and vendors. Work closely with engineering leads to manage schedule, risks, milestones, and tapeout readiness.

Hybrid role based in Mountain View with in-office presence required Tuesdays–Thursdays.

Experience Level

Senior — typically 10+ years of technical program management or silicon/SoC program leadership experience.

Responsibilities

You will manage program execution, risk, and communication for SoC physical design efforts.

• Own program milestones, dependencies, critical path, and tapeout readiness across PD, RTL, verification, validation, and supply chain.
• Develop program playbooks, trackers, risk registers, and executive dashboards.
• Drive gate reviews, weekly program syncs, and issue escalations; coordinate closure of technical actions.
• Manage technical risks related to design maturity, IP readiness, verification closure, physical signoff, and package/test readiness.
• Coordinate pre-silicon execution through tapeout, silicon bring-up, debug, qualification, and yield learning.
• Support trade-off analysis across performance, power, area, cost, reliability, and manufacturability.
• Prepare executive-level updates on milestone health, top risks, decisions required, and resource gaps.

Requirements

Must-have technical program management and silicon program experience; list focuses on essential skills and tools.

• 10+ years managing technical programs in silicon/SoC development through multiple silicon lifecycle phases.
• Proven experience coordinating complex cross-functional programs with multiple engineering teams, external vendors, and tight schedules.
• Hands-on familiarity with ASIC/SoC flows: architecture planning, RTL design, functional verification, synthesis, DFT, physical design, timing closure, signoff, and tapeout.
• Experience with pre-silicon validation platforms (simulation, emulation, FPGA prototyping, or hardware/software co-validation).
• Strong technical judgment to manage trade-offs across performance, power, area, cost, schedule, quality, and risk.
• Technical fluency to follow RTL milestones, DV sign-off, PD handoffs, and silicon bring-up without translation.
• Proven ability to drive schedules, dependency management, risk registers, and executive communication.
• Proficiency with program-management and collaboration tools such as Jira, GitHub, Confluence, Smartsheet, MS Project, or Google Workspace.
• Authorization to work in the United States and ability to work onsite in Mountain View Tuesdays–Thursdays.
• Role requires handling export-controlled information; employment contingent on compliance with U.S. export control laws.

Nice-to-have:

• Experience with AI infrastructure, datacenter racks, networking, storage systems, or high-power servers.
• Experience coordinating programs involving high-speed interconnects, liquid cooling, telemetry, diagnostics, or rack-scale validation.
• Prior hands-on engineering experience in back-end physical design.

Education Requirements

Not specified.

About the Company

Company: MatX

Headquarters: Mountain View, California, USA

MatX specializes in creating faster chips for large language models (LLMs), focusing on innovative hardware and software solutions. The company fosters a collaborative and supportive work environment, welcoming candidates of all experience levels. Their approach prioritizes deep understanding and consideration of novel methods to drive efficiency and performance in their projects, particularly in silicon design and related engineering roles.