Technical Program Manager, Silicon

Job Title

Technical Program Manager, Silicon

Role Summary

Lead end-to-end execution of a custom silicon program from architecture definition through tapeout, first-silicon bring-up, and production ramp. Partner with front-end design, verification, physical design, DFT, analog/mixed-signal, foundry, and packaging teams and external vendors.

The role emphasizes program ownership, external partner management, execution tooling, and AI-assisted program management approaches.

Experience Level

Senior — typically requires 8+ years of silicon/SoC program management or equivalent experience owning chip schedules end to end.

Responsibilities

Own and drive the integrated silicon program and external partnerships; build lightweight execution mechanisms and run post-silicon activities.

• Own the integrated program plan: architecture closure, RTL freeze, DV milestones, IP delivery, PD closure, DFT, tapeout, and post-silicon bring-up.
• Manage external partners: ASIC design houses, IP vendors, foundry, OSAT, and packaging/test vendors.
• Run technology and IP selection processes: evaluate vendors, track candidates, and drive build/buy/license decisions.
• Define and maintain milestone definitions, risk and dependency tracking, design reviews, release management, and executive reporting.
• Coordinate hardware-system and software teams to ensure design trade-offs are coordinated and communicated.
• Plan and execute post-silicon activities: bring-up planning, ATE/test handoff, sample distribution, validation, and production ramp.
• Develop and share AI-assisted program management methods for scheduling, dependency modeling, and status synthesis.

Requirements

Must-have experience and skills for immediate effectiveness on a silicon program.

• 8+ years in silicon/SoC program management, chip lead, or equivalent role with end-to-end chip schedule ownership.
• Direct ownership of at least one program that taped out and reached production, with specific milestone accountability and lessons learned.
• Technical fluency across the silicon lifecycle: front-end, DV, physical design, DFT, foundry, and packaging.
• Experience managing external silicon partners, including SOW scoping, delivery tracking, and escalation.
• Track record building program mechanisms from scratch in ambiguous, fast-moving contexts.
• Strong written communication for plans, reviews, and executive updates.
• Comfort operating with high autonomy and limited existing process.

Nice-to-have:

• Experience with ML accelerators, high-performance compute, networking, or large high-bandwidth SoCs at advanced nodes.
• Experience on first-generation or early-silicon programs, standing up flows or vendor relationships.
• Hands-on engineering background in design, DV, PD, DFT, or SI/PI.
• Experience with hardware-software co-design and working with compiler/kernel/runtime teams.
• Practical experience using AI tools in program workflows.

Education Requirements

Bachelor's or Master's degree in EE, CE, CS, or a related technical field is listed as expected; equivalent combination of education and experience is acceptable. The posting explicitly states "BS/MS in EE, CE, CS, or a related field, or equivalent experience" and notes a minimum of a bachelor’s degree or equivalent training/experience.

About the Company

Company: Anthropic

Headquarters: San Francisco, CA, United States

Anthropic is an AI research and safety company developing reliable, interpretable, and steerable large language models (Claude) and related tools, focusing on alignment, reinforcement learning, and scalable infrastructure for safe AI deployment.