Principal ASIC Design Engineer (Silicon Engineering)

Job Title

Principal ASIC Design Engineer (Silicon Engineering)

Role Summary

Design and deliver RTL and micro-architecture for next-generation ASICs used in SpaceX Starlink space and ground systems. Work across systems, firmware, architecture, verification, and physical implementation teams to produce production silicon.

Responsible for producing synthesis- and timing-clean RTL, supporting timing closure and physical implementation, and participating in silicon bring-up and validation.

Experience Level

Senior — 10+ years of experience in RTL implementation and ASIC design.

Responsibilities

Primary responsibilities include architecture trade-offs, RTL implementation, verification collaboration, and silicon delivery.

• Evaluate architectural trade-offs based on features, performance, and system constraints.
• Define micro-architecture and implement RTL in Verilog/SystemVerilog; integrate into top level.
• Deliver fully verified, synthesis- and timing-clean designs.
• Work closely with verification to ensure functional coverage and correctness.
• Provide timing constraints and support physical implementation (synthesis, timing closure, formality checks).
• Participate in silicon bring-up and hardware validation.

Requirements

Must-have skills and constraints; preferred skills listed separately.

• 10+ years of hands-on RTL implementation experience using Verilog/SystemVerilog.
• Proven ability to deliver synthesis- and timing-clean RTL and integrate IP into top-level designs.
• Experience creating timing constraints and supporting synthesis and timing closure activities.
• Experience with silicon bring-up and hardware validation.
• ITAR eligibility: must be a U.S. citizen, U.S. lawful permanent resident (green card), refugee, asylee, or otherwise eligible to obtain required U.S. Department of State authorizations (ITAR guidance).
• Ability to work extended hours or weekends as needed for mission-critical deadlines.

Nice-to-have:

• Experience solving clock domain crossing and power-optimization challenges.
• ASIC/SoC system integration and embedded CPU subsystem experience.
• Familiarity with standard bus protocols (AXI, AHB) and high-speed/low-power design techniques.
• Scripting skills (Python) and experience with EDA tools (HDL simulators, lint tools).
• Strong teamwork and communication skills for cross-disciplinary collaboration.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science (specified in posting).

About the Company

Company: SpaceX

Headquarters: Hawthorne, California, United States

SpaceX is focused on developing space technologies to enable human exploration of Mars and beyond. The company is known for its advancements in rocketry and its Starlink satellite constellation, which delivers high-speed internet globally.