Technical Director, DFT

Job Title

Technical Director, DFT

Role Summary

Lead the definition and implementation of DFT architectures and methodologies for advanced SoC designs within the MCU/MPU Engineering organization. Work across design, verification, physical design, and test engineering to ensure high test coverage, manufacturability, and efficient production test development.

Experience Level

Senior level. The role requires leadership and mentoring experience; the posting does not specify exact years of experience.

Responsibilities

Key responsibilities include:

• Develop and implement DFT architectures and methodologies to achieve high test coverage and reduced test time for advanced SoCs.
• Drive DFT strategy and planning for new projects and integrate DFT solutions into the overall design flow.
• Lead DFT implementation activities: scan insertion, ATPG, BIST, and boundary-scan (JTAG) insertion.
• Perform DFT verification and sign-off: scan-chain simulations, stuck-at and transition-fault simulations, and DFT coverage analysis.
• Collaborate with Test Engineering on manufacturing test bring-up and production test program development.
• Investigate and resolve DFT-related issues during silicon bring-up and production testing with cross-functional teams.
• Drive continuous improvement of DFT methodologies and mentor junior engineers on best practices.

Requirements

Must-have technical skills and attributes, plus desirable additions:

• Must-have: Significant industry experience in DFT engineering for complex SoC designs.
• Must-have: Proficiency with industry DFT tools such as Mentor, Tessent, Synopsys DFT Compiler, and Cadence Encounter Test.
• Must-have: Strong expertise in DFT architectures and techniques including scan insertion, ATPG algorithms, BIST architectures, and boundary-scan (JTAG).
• Must-have: Experience with DFT verification methodologies and tools (simulation-based and formal), fault modeling, and coverage analysis.
• Must-have: Familiarity with industry standards such as IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG).
• Must-have: Proven leadership, communication skills, and experience mentoring junior engineers.
• Nice-to-have: Experience with Siemens Scan Streaming Network (SSN).
• Nice-to-have: Experience with hierarchical DFT, low-power DFT, DFT automation and scripting (TCL, Perl, Python), or post-silicon activities such as test-pattern compression and silicon bring-up.

Education Requirements

Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related field is listed as a preferred qualification.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.