System Level Test Engineer

Job Title

System Level Test Engineer

Role Summary

Hands-on validation engineer responsible for system-level silicon validation of DDR, LPDDR, and HBM memory interface IP in a lab environment. Work closely with firmware and design teams to bring up silicon, characterize margins, debug failures, and scale test automation across product generations.

Experience Level

Mid-level - typically 3–5 years of relevant silicon validation, system-level lab debug, or applications experience.

Responsibilities

Execute and document system-level silicon validation across controller, PHY, and attached memory devices; provide reproducible debug and test automation.

• Plan and perform system-level validation of DDR, LPDDR, and HBM IP on silicon, including controller, PHY, and memory device interactions.
• Bring up new silicon and reference platforms: power, clocks, reset, training, link-up, and initial read/write traffic.
• Measure and characterize data eye, setup/hold, CA and DQ timing, voltage-frequency shmoo, and thermal corners versus JEDEC/IP spec.
• Debug failures using oscilloscopes, VNAs, BERTs, logic/protocol analyzers, and on-chip status (training logs, error counters, registers).
• Isolate root causes across silicon, package, interposer/substrate, board, DRAM/HBM device, firmware, and test setup.
• Automate validation and characterization pipelines (e.g., GitLab) to scale tests across PVT corners and releases.
• Write validation plans, test reports, and clear bug/errata entries; track issues to closure across silicon spins.
• Support customer system debug when failures map to IP behavior and feed lab findings into subsequent IP drops and test content.
• Maintain golden boards, interposer/substrate setups, instrument configurations, and reusable test scripts.

Requirements

Must-have technical skills and experience for immediate contribution. Nice-to-have items are listed separately.

• Must-have: 3–5 years of silicon validation, applications, or system-level lab debug of memory interfaces.
• Must-have: Hands-on silicon or board bring-up experience (power, clocks, reset, training).
• Must-have: Practical knowledge of DRAM protocols and training behavior (command/address, DQ/DQS/WDQS, ranks, bursts, refresh).
• Must-have: Lab instrumentation skills: high-bandwidth oscilloscope, BERT, power analyzer, DMM; experience capturing and interpreting measurement data.
• Must-have: Scripting to drive DUT and instruments (Python preferred) and to automate test flows.
• Must-have: Ability to read JEDEC timing tables, DRAM/HBM datasheets, board/substrate notes, and IP programming guides and convert them into tests.
• Must-have: Strong debugging and reporting skills that identify failing condition, evidence, and ownership (design, verification, package, board, or memory vendor).
• Must-have: Basic signal-integrity understanding for DQ, DQS, and CA (ISI, crosstalk, reflections, probe loading) and how layout/interposer routing affects signals.
• Must-have: Familiarity with interposer or CoWoS-style assembly constraints, lane repair, and thermal gradients across stacks.
• Nice-to-have: Experience building CI/CD-style validation pipelines and scaling automation across products; prior customer-facing debug experience.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.