Design Verification Engineer II
Silicon LabsJob Title
Design Verification Engineer II
Role Summary
Work on verification for Wireless MCU SoCs within the IoT Digital Design team. The role focuses on developing verification plans, building SystemVerilog/UVM testbenches, and driving coverage and regression for SoC and IP blocks, including mixed-signal areas.
Team responsibilities include RTL architecture/verification, firmware collaboration, and pre-silicon (and occasional post-silicon) debug. Office is located in Singapore (above Tai Seng MRT); role follows a hybrid schedule.
Experience Level
Mid-level engineer. The posting requests approximately 5–10+ years of verification experience.
Responsibilities
Primary responsibilities include planning, implementing, and executing verification for SoC/IP blocks and supporting debug and automation.
- Develop and execute verification plans for SoC, IP blocks, and mixed-signal designs.
- Design and maintain SystemVerilog/UVM-based testbenches; create directed and constrained-random tests.
- Drive functional coverage closure, write assertions (SVA), and analyze regression results.
- Debug RTL and verification failures across simulation and emulation environments; support pre-silicon and occasional post-silicon debug.
- Collaborate with RTL designers, architecture, firmware/software, and validation teams.
- Improve verification methodologies, automation, and CI flows.
- Mentor junior engineers and contribute to verification strategy.
Requirements
Must-have technical skills and practical verification experience. Education requirements are summarized separately below.
- 5–10+ years of design verification experience focused on SoC/IP verification.
- Strong SystemVerilog and UVM/OVM experience; experience building and running UVM testbenches.
- Practical RTL and gate-level simulation and debug experience.
- Experience with functional coverage and assertions (SVA); ability to drive coverage closure.
- Familiarity with AMBA protocols (AXI/APB) and embedded/MCU subsystems.
- Scripting skills (Python, Tcl, Perl) for testbench automation and flows.
- Experience creating directed and constrained-random test cases and managing regressions.
- Ability to collaborate across RTL, architecture, firmware, and validation teams and to mentor junior engineers.
- Nice-to-have: wireless SoC experience, low-power verification concepts, CDC/RDC verification, and mixed-signal/AMS verification experience.
Education Requirements
BS or MS in Electrical Engineering or Computer Engineering (explicitly listed as BS/MS in the posting).
About the Company
Company: Silicon Labs
Headquarters: Austin, Texas, USA
Silicon Labs is a leading innovator in low-power wireless connectivity, creating embedded technology that connects devices to improve lives. With a focus on advanced edge connectivity applications, the company provides device makers with cutting-edge solutions and support. Headquartered in Austin, Texas, Silicon Labs operates in over 16 countries, serving markets such as smart home, industrial IoT, and smart cities.
