System IP Design Engineer (India)

Job Title

System IP Design Engineer (India)

Role Summary

Hands-on RTL Design Engineer responsible for the microarchitecture and RTL implementation of power-management and system IP blocks such as the Power Management Subsystem, Interrupt Controllers, AXI Interconnect, and Cache Controller. The role works across architecture, firmware, software, design verification, and physical design teams to define and optimize power and performance for RISC-V/ARM-based SoCs.

Experience Level

Mid-level — typical experience 3–6 years in ASIC/RTL design. Candidates at other seniorities may be considered during interview and offered an appropriate level.

Responsibilities

The engineer will own microarchitecture and RTL delivery for key system IP and drive tasks required to bring design to silicon.

• Define microarchitecture and implement RTL for power-management subsystems, interrupt controllers, AXI interconnects, and cache controllers.
• Collaborate with architecture, firmware, software, DV, and PD teams to specify and validate power-management solutions.
• Drive verification closure, functional debug, performance debug, synthesis, timing closure, and power optimization.
• Author and run LINT, CDC/RDC, and power-intent checks; address and close related issues.
• Use DV and analysis tools (e.g., Verdi, NCSIM) and power-estimation flows to validate designs.
• Develop and apply design-for-power, debug, and test methodologies; support silicon bring-up.
• Mentor junior engineers and support cross-functional design reviews and integration activities.

Requirements

Must-have technical skills and practical experience required to perform the role, followed by desirable skills.

Must-have

• 3–6 years of ASIC design experience with microarchitecture and RTL for complex subsystems.
• Proficient in Verilog/SystemVerilog for design and debug.
• Strong understanding of power-management concepts: clocking, reset, DVFS, and low-power modes.
• Experience with standard bus protocols (AXI, AHB, APB, CHI) and SoC subsystem integration.
• Experience driving verification closure, synthesis, timing, and power optimizations.
• Familiarity with LINT, CDC/RDC, power-intent checks and common DV/analysis tools (e.g., Verdi, NCSIM) and power estimation tools.

Nice-to-have

• Hands-on experience with cache controllers, AXI interconnect design, interrupt controllers or power-management subsystems.
• Knowledge of functional safety practices (ISO 26262) in hardware design.
• Experience with silicon bring-up and cross-domain performance/power optimization.
• Leadership or mentorship experience.

Education Requirements

Not specified.

About the Company

Company: Tenstorrent

Headquarters: Austin, Texas, United States

Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.