System IP Design Engineer (Bengaluru, India)
TenstorrentJob Title
System IP Design Engineer — Bengaluru, India
Role Summary
Hands-on RTL engineer responsible for the microarchitecture and RTL implementation of power-management and system IP blocks (Power Management Subsystem, Interrupt Controllers, AXI interconnects, and Cache Controller) for next-generation RISC-V/ARM SoCs. Work closely with architecture, firmware, software, design verification, and physical design teams to define, implement, and optimize these subsystems.
This is a hybrid role based in Bengaluru, India.
Experience Level
Mid-level — hiring range stated at 5–10 years of ASIC/SoC/IP design experience. Candidates will be evaluated and placed at an appropriate level during interview.
Responsibilities
Primary responsibilities include design, implementation, and cross-functional delivery of system IP blocks:
- Own microarchitecture definition and RTL development for Power Management Subsystem, Interrupt Controllers, AXI interconnect, and Cache Controller.
- Write and maintain clean, synthesizable RTL (Verilog/SystemVerilog); perform design reviews and code-quality checks.
- Collaborate with verification on assertions, test plans, debug, and coverage closure.
- Drive synthesis, timing closure, power optimization, and performance/debug workstreams.
- Design for low-power operation: clocking, reset, DVFS, low-power modes, and power intent integration.
- Develop and optimize large pipelined, stateful, and high-speed designs including interconnects and memory subsystems.
- Work with DV, PD, firmware, and software teams from design through silicon bring-up.
Requirements
Key technical requirements and desirable skills.
- 5–10 years of ASIC/SoC/IP design experience with hands-on microarchitecture and RTL development.
- Proficient in Verilog/SystemVerilog and RTL design/debug practices.
- Practical experience with power-management concepts: clocking, reset, DVFS, and low-power modes.
- Experience with on-chip interconnects, NoC, AXI/AHB/APB protocols and cache/memory subsystem IP.
- Experience driving verification closure, synthesis, timing closure, and power/performance optimization.
- Familiarity with lint, CDC/RDC, and power-intent checks and flows.
- Proficiency with verification and analysis tools (examples: Verdi, NCSIM) and power estimation tools.
- Strong problem-solving, attention to detail, and communication skills; ability to collaborate across teams.
- Nice-to-have: awareness of functional safety (ISO 26262), experience with RAS/QoS fabrics, PCIe/IO, and prior mentorship or leadership of junior engineers.
Education Requirements
Not specified.
About the Company
Company: Tenstorrent
Headquarters: Austin, Texas, United States
Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.
