System IP Design Engineer

Job Title

System IP Design Engineer

Role Summary

Own the microarchitecture and RTL implementation of the Power Management Subsystem, Interrupt Controllers, AXI Interconnect, and Cache Controller for next-generation RISC-V/ARM SoCs. Work on design, implementation, optimization, and handoff to verification, synthesis, and bring-up teams.

Collaborate with architecture, firmware, software, design verification (DV), and physical design (PD) teams to meet performance, power, area, and manufacturability targets. This position is hybrid, based in Bengaluru, India.

Experience Level

Mid-level — typically 5–10 years of ASIC/SOC/IP design experience; level will be calibrated during interview.

Responsibilities

Key responsibilities include:

• Define microarchitecture and deliver RTL for power management, interrupt controllers, AXI interconnect, and cache controller IPs.
• Implement RTL (Verilog/SystemVerilog) with attention to performance, power, and area trade-offs.
• Drive synthesis, timing closure, power optimization, and implementation debug.
• Collaborate with verification on assertions, test plans, debug, and coverage closure.
• Perform linting, CDC/RDC analysis, and power-intent (UPF/CPF) checks.
• Work on high-speed pipelined and stateful designs, and on low-power/clocking/reset/DVFS schemes.
• Support silicon bring-up and cross-functional integration activities.

Requirements

Must-have and relevant skills:

• Must-have: 5–10 years experience in ASIC/SoC/IP design with hands-on microarchitecture and RTL development.
• Must-have: Strong RTL coding skills in Verilog/SystemVerilog and experience across design, debug, and analysis.
• Must-have: Deep understanding of power management (clocking, reset, DVFS, low-power modes) and design-for-power methodologies.
• Must-have: Experience with on-chip interconnects, AXI/AHB/APB/CHI protocols, NoCs, caches, cache coherency, and memory subsystems.
• Must-have: Experience driving verification closure, synthesis, timing closure, and power/performance optimization.
• Must-have: Proficiency with lint, CDC/RDC checks, power intent (UPF/CPF) flows and with DV/analysis tools (examples: Verdi, NCSIM) and power-estimation tools.
• Nice-to-have: Familiarity with RAS designs, QoS in fabrics, PCIe/IO subsystems.
• Nice-to-have: Awareness of functional safety practices (ISO 26262) in hardware design.
• Strong problem-solving, attention to detail, and communication/collaboration skills.

Education Requirements

Not specified.

About the Company

Company: Tenstorrent

Headquarters: Austin, Texas, United States

Tenstorrent is a technology company focused on designing innovative computing solutions. They are known for their expertise in the development of advanced hardware, including ASICs and SoCs, aimed at enhancing performance and efficiency in various applications.