Synthesis & Static Timing Analysis (STA) Engineer
VoltaiJob Title
Synthesis & Static Timing Analysis (STA) Engineer
Role Summary
The STA Engineer owns RTL-to-netlist timing closure and sign-off for complex ASIC blocks and full-chip designs. You will run synthesis flows, develop constraints, perform STA signoff, and build automation to improve throughput and reliability.
Work directly with RTL, physical design, and verification teams and evaluate AI-generated constraints and fixes.
Experience Level
Mid-level. Requires 5+ years of synthesis and STA experience on production tapeouts.
Responsibilities
Primary responsibilities include:
- Develop and maintain logic synthesis flows and SDC constraints for blocks and full chips.
- Drive timing closure across corners and modes in collaboration with RTL and physical design teams.
- Run and sign off STA, including on-chip variation, crosstalk, and multi-corner multi-mode analysis.
- Perform logic equivalence checking between RTL and netlist.
- Build automation and scripts to make synthesis and timing flows faster and more reliable.
- Evaluate AI-generated constraints and timing fixes and help define quality criteria.
Requirements
Must-have qualifications:
- 5+ years of synthesis and STA experience on production tapeouts.
- Hands-on experience with Design Compiler/Fusion Compiler or Genus, and PrimeTime or Tempus.
- Strong SDC skills: clocks, exceptions, generated clocks, and multi-mode constraints.
- Experience with logic equivalence checking tools (Formality or Conformal).
- Proficient in Tcl and Python scripting.
Nice-to-have:
- Advanced-node experience (7nm and below).
- Experience with ECO flows and timing signoff methodology.
- Interest or experience with AI-assisted design tools.
Education Requirements
Not specified.
About the Company
Company: Voltai
Headquarters: Palo Alto, CA, United States
Voltai develops AI-driven world models and agents to design, evaluate, and optimize physical systems-focusing on hardware, electronics, and semiconductors to enable AI-led hardware co-design, performance modeling, and cross-domain optimization.
