Static Timing Analysis Engineer

Job Title

Static Timing Analysis Engineer

Role Summary

Develop timing constraints and perform timing-closure signoff for low-power wireless SoCs and mixed-signal IP. The role focuses on timing constraint development, static timing analysis flow improvement, timing signoff criteria, and cross-functional collaboration to resolve complex timing issues.

Experience Level

Level: Senior. The role expects 8+ years of relevant experience.

Responsibilities

Key responsibilities include timing closure activities at both IP and SoC levels and improving static timing analysis methodologies.

• Develop timing constraints at IP and SoC levels in collaboration with designers.
• Improve and evolve static timing analysis flows and methodologies.
• Define timing signoff criteria (aging, on-chip variation, signal integrity).
• Analyze timing reports using scripting to generate insights and accelerate closure.
• Collaborate with global design and cross-functional teams to resolve complex static timing issues.
• Drive timing closure for mixed-signal IP integration.

Requirements

Must-have skills and experience.

• 8+ years of relevant industry experience in timing closure and static timing analysis.
• Deep knowledge of timing closure flow and methodology.
• Experience developing timing constraints for functional and test modes (e.g., scan).
• Hands-on experience with static timing tools such as Synopsys PrimeTime or Siemens/Ansys Tempus.
• Proficient scripting skills (Perl, Python, Tcl, shell) for report analysis and automation.
• Knowledge of timing modes and corners, and signoff considerations (aging, on-chip variation, SI).
• Familiarity with low-power design techniques (clock gating, power gating, DVFS).
• Experience with timing model generation for mixed-signal IP and design flows (Lint, CDC, Synthesis, Logic Equivalence, DFT, Place and Route).
• Experience with Verilog and SystemVerilog.

Nice-to-have: experience with multi-core/multi-threaded SoCs, multi-level cache subsystems, or wireless protocol stacks.

Education Requirements

Bachelor's or master's degree in Electrical Engineering or Computer Engineering is listed as the degree requirement. The posting also specifies 8+ years of relevant experience.

About the Company

Company: Silicon Labs

Headquarters: Austin, Texas, USA

Silicon Labs is a leading innovator in low-power wireless connectivity, creating embedded technology that connects devices to improve lives. With a focus on advanced edge connectivity applications, the company provides device makers with cutting-edge solutions and support. Headquartered in Austin, Texas, Silicon Labs operates in over 16 countries, serving markets such as smart home, industrial IoT, and smart cities.