Synthesis STA Engineer

Role Overview

As part of the Physical Aware group at Advanced Micro Devices, this role involves collaborating with various departments to enhance the performance of sophisticated IPs. You will interface frequently with architecture, IP design, physical design teams, and product engineers to ensure optimal quality and power-performance-area (PPA) metrics for complex integrated circuits.

Experience Level

This position is targeted at seasoned professionals with significant experience in the field of silicon design engineering, specifically focusing on synthesis, static timing analysis (STA), and layout extraction (LEC).

Job Responsibilities

The main responsibilities for this position include:

• Conducting synthesis for complex and high-speed IPs while developing comprehensive constraints.
• Demonstrating strong hands-on capabilities in synthesis and STA processes.
• Utilizing Conformal flow and LEC effectively for design verification.
• Providing constructive feedback to the RTL team to guide physically-driven architectural modifications.
• Managing shared data for collaborative design efforts across multiple projects.
• Coordinating with multiple system-on-chip (SoC) teams on complex IP design.
• Engaging in physical-aware activities including floorplanning, placement, clock tree synthesis, and routing.
• Leading and mentoring junior team members in technical domains.

Qualifications

Applicants must possess a comprehensive understanding of physical design, STA, and the synthesis design cycle, complemented by the following preferences:

• A minimum of 15 years of experience in synthesis, STA, or LEC domains.

Education Requirements

The candidate should have either a Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.