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Synthesis - Lead / Staff Engineer

Qualcomm
September 04, 2026
Full-time
On-site
Chennai, Tamil Nadu, India
RTL Design Jobs, Level - Senior

Job Title

Synthesis - Lead / Staff Engineer

Role Summary

Responsible for synthesis and low-power implementation bring-up of power-complex SoCs. The role works within the Hardware Engineering / Physical Implementation teams to deliver power-aware synthesis flows, resolve implementation issues, and ensure timing and low-power qualification at SoC and subsystem levels.

Experience Level

Level: Senior. The posting indicates an expectation of experienced candidates (7+ years noted). See Education Requirements for degree-plus-experience alternatives.

Responsibilities

Primary responsibilities include technical implementation, verification, and cross-team collaboration on synthesis and low-power flows.

  • Lead synthesis and low-power implementation for multi-voltage, power-complex SoCs.
  • Apply physical- and power-aware synthesis techniques; balance power, performance, area, and verification priorities.
  • Identify pre-layout timing challenges and provide constraint feedback to design teams.
  • Perform pre- and post-layout netlist low-power qualification at flat and subsystem levels.
  • Collaborate closely with DFT teams for MBIST and scan insertion support.
  • Work with Physical Design to identify and fix low-power implementation issues.
  • Develop and maintain automation and analysis scripts (TCL, Perl, Python, shell).
  • Mentor junior engineers on timing flows and synthesis methodologies.

Requirements

Must-have technical skills and experience; nice-to-have items listed separately.

  • Must-have: Proven experience with physical- and power-aware synthesis and low-power implementation for multi-voltage designs.
  • Experience qualifying pre- and post-layout netlists and addressing timing and low-power issues at SoC/subsystem level.
  • Strong scripting ability (TCL, Perl, Python, shell) for flow automation and analysis.
  • Experience collaborating with Physical Design and DFT teams to resolve implementation and testability issues.
  • Practical knowledge of timing closure challenges on advanced process nodes and mitigation approaches.
  • Nice-to-have: Experience with design data management tools (Perforce, ClearCase), logical equivalence checking (RTL-to-netlist, netlist-to-netlist), timing derating techniques, and prior mentoring experience.

Education Requirements

Posting specifies degree-plus-experience alternatives: Bachelor's in Computer Science, Electrical/Electronics Engineering, Engineering or related field (with 3+ years hardware engineering experience); OR Master's in those fields (with 2+ years experience); OR PhD in those fields (with 1+ year experience). The posting also notes an expectation of 7+ years of experience for this role. No certifications were specified.


About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.

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Date Posted: 2026-09-04