Synthesis Engineer (Lead/Staff/Sr Staff)

Job Title

Synthesis Engineer (Lead/Staff/Sr Staff)

Role Summary

Lead a team responsible for synthesis and implementation of Display Sub-System blocks, driving timing closure, low-power implementation, and signoff-quality constraints. Collaborate with RTL, DFT, physical design and verification teams to deliver high-quality netlists for complex multi-clock designs.

Experience Level

Senior level. Typical experience for this role is approximately 9–13+ years of relevant hardware implementation or synthesis experience.

Responsibilities

The role focuses on synthesis, timing and low-power implementation for complex blocks and on leading a small team of engineers.

• Lead implementation projects and mentor team members; manage multiple time-critical, complex projects.
• Create and validate signoff-quality synthesis and timing constraints for complex multi-clock blocks.
• Perform synthesis, logical equivalence checking (LEC), low-power checks, and memory BIST insertion.
• Develop and validate power intent (UPF) and other low-power constraints; run low-power flows.
• Run RTL lint, CLP, MEMBIST, DFT DRC and related quality checks as needed.
• Develop and maintain TCL/perl/python scripts for flow automation, analysis and debugging.
• Work with design, DFT and physical design teams for netlist delivery and timing closure; handle ECOs and formal verification issues.
• Drive area, power and performance optimization and implement pipelining or other micro-architectural fixes for timing closure.

Requirements

Must-have technical skills and leadership capabilities are listed below; items labeled "Nice-to-have" are beneficial but not required.

• Must-have: Strong understanding of physical synthesis methodologies and timing closure for multi-clock domain designs.
• Must-have: Hands-on experience with industry synthesis and STA tools (e.g., Synopsys Genus/DCG/Fusion Compiler and Synopsys PrimeTime).
• Must-have: Experience writing timing constraints for synthesis and STA, and performing timing optimization and pipelining.
• Must-have: Familiarity with low-power implementation flows using UPF and power optimization techniques such as clock gating.
• Must-have: Scripting experience (Perl, Python, TCL) for automation and flow development.
• Must-have: Experience handling ECOs, constraints validation, and working with design/DFT/PD teams to deliver production-quality netlists.
• Nice-to-have: Hands-on experience with Cadence Conformal LEC and Conformal Low Power.
• Nice-to-have: Experience with RTL development or physical design and memory BIST flows.

Education Requirements

Degree required: Bachelor's, Master's or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a closely related technical field. The posting allows degree-plus-experience combinations (e.g., BS + 4+ years, MS + 3+ years, PhD + 2+ years) and indicates equivalent practical experience is acceptable. For this senior lead role, the expectation is roughly 9–13+ years of relevant engineering experience.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.