Substrate Packaging Defect Metro Tool Owner

Job Title

Substrate Packaging Defect Metro Tool Owner

Role Summary

Join the SPTD Yield team as a Defect Metrology Engineer supporting substrate and assembly test manufacturing (ATM) for advanced packaging technologies including EMIB-T, glass core, EMIB scaling, and panel-level packaging. The role focuses on defect inspection, tool ownership, yield improvement, and cross-functional collaboration to meet program deliverables.

Experience Level

Mid-level. Typical experience expectation is roughly 1–3 years of semiconductor industry experience depending on degree (see Education Requirements for degree/experience combinations).

Responsibilities

Key day-to-day responsibilities and deliverables:

• Use defect inspection tools to detect, diagnose, and resolve process issues in collaboration with defect reduction, process integration, and module teams.
• Perform real-time data analysis, DOE summaries, reporting, and present findings to guide yield improvements and decision-making.
• Lead next-generation tool installations and milestones: purchase/spec development, source inspection, design, pre-fac, safety approvals, supplier and Intel qualification.
• Establish and roll out procedures and equipment setups for defect metrology tools to meet quality and WIP velocity targets.
• Connect new tools to automation and yield-analysis systems; set up data flows and ensure reliable performance and data integrity.
• Develop equipment roadmaps and collaborate with suppliers and supply-chain partners on software/hardware upgrades and feature improvements.
• Prepare and deliver technical presentations on tool and system capabilities to leadership and stakeholders.
• Create visualizations, dashboards, and analyses; detect and correct data anomalies; communicate insights clearly to support operational decisions.

Requirements

Must-have skills and experience (education details are under Education Requirements):

• Proven experience in micro-contamination management in a semiconductor manufacturing environment.
• Experience as a Yield Analyst, defect-reduction owner, or defect-metrology tool owner with demonstrated tool ownership responsibilities.
• Strong programming skills in Python for data analysis, automation, and tooling integration.
• Experience with tool installation/qualification, supplier interaction, and cross-functional project leadership.
• Ability to work independently, proactively identify issues, and lead yield-enhancement initiatives.
• Competence in descriptive statistics, data visualization, and building dashboards or presentations to communicate results.

Nice-to-have:

• Knowledge of statistical methods and experimental design (DOE) applied to tool qualification and process development.
• Demonstrated understanding of semiconductor process flows and defect metrology assessment based on process requirements.

Education Requirements

Degree options and associated semiconductor experience as stated in the posting: Bachelor's degree in Electrical Engineering, Chemical Engineering, Optical Engineering, Materials Science, Physics, or a related field plus 3 years semiconductor experience; OR Master's degree in those fields plus 2 years semiconductor experience; OR PhD in those fields plus 1+ years semiconductor experience. The posting also notes relevant experience may come from industry work, internships, coursework, or research.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.