Substrate IC Package Layout Design Engineer

Job Title

Substrate IC Package Layout Design Engineer

Role Summary

Design and deliver complex IC substrate packages for high-power, high-speed AI processors and accelerators. The role covers end-to-end substrate layout: power delivery, high-speed routing, verification, and manufacturability, working closely with silicon, SI/PI, packaging, and OSAT partners.

Experience Level

Senior-level. The team is seeking candidates with extensive experience; the posting requests 10+ years in IC substrate layout design.

Responsibilities

Primary responsibilities focus on substrate layout, signal and power integrity, and integration with chip and manufacturing teams.

• Lead design and development of large, multi-layer IC substrate layouts (>50mm) with high pin counts and dense routing.
• Architect and optimize power delivery networks to support high-power custom silicon (>700W).
• Develop high-speed signal routing solutions and mitigate signal integrity issues for signaling beyond 50GHz.
• Optimize CoWoS interposer and substrate integration for thermal and electrical performance.
• Perform DRC and LVS verification and maintain design rule compliance.
• Create and maintain design documentation, guidelines, and layout constraints.
• Collaborate with silicon, SI/PI, packaging, manufacturing, and OSAT teams to ensure manufacturability and feasibility.
• Participate in design reviews and mentor junior engineers.

Requirements

Expect strong, demonstrable experience in substrate layout for high-performance processors. Below are the core qualifications and useful additions.

• Must-have: 10+ years of experience in IC substrate/layout design for high-performance processors or accelerators.
• Must-have: Proven experience with large substrate packages (>50mm) and high-density layouts.
• Must-have: Proven experience designing package power delivery capable of supporting >700W solutions.
• Must-have: Expertise in high-speed signaling design and mitigation of SI issues for >50GHz signaling (crosstalk, reflections, impedance control).
• Must-have: Advanced proficiency with Allegro Package Designer, including constraint management, routing, and verification.
• Must-have: Deep understanding of SI/PI principles applied at the package/substrate level.
• Nice-to-have: Prior experience optimizing CoWoS/interposer designs and working directly with OSAT vendors on manufacturability and process constraints.
• Nice-to-have: Experience driving thermal/electrical trade-offs and detailed design-for-manufacturing (DFM) considerations.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Etched

Headquarters: San Jose, CA, United States

Etched develops purpose-built AI inference ASICs and systems optimized for transformer models, aiming to deliver significantly higher performance, lower cost, and lower latency than GPUs. The company focuses on enabling applications like real-time video generation and advanced reasoning agents, and is backed by leading investors and engineers.