Substrate IC Package Layout Design Engineer

Job Title

Substrate IC Package Layout Design Engineer

Role Summary

Lead the layout design of complex IC substrate packages for high-power, high-speed AI processors and accelerators. Work on cross-functional teams including chip design, packaging, SI/PI, and manufacturing to deliver large multi-layer substrates with attention to power delivery, signal integrity, thermal performance, and manufacturability.

Experience Level

Senior — typically 10+ years of relevant IC substrate or package layout design experience; equivalent practical experience will be considered.

Responsibilities

Primary responsibilities include design, verification, and coordination to produce manufacturable substrate layouts for advanced processors.

• Lead design of large (>50 mm), multi-layer substrate packages with high pin counts and dense routing.
• Architect and implement power delivery networks capable of supporting >700 W package power requirements.
• Develop high-speed routing solutions to support >50 GHz signaling and minimize signal integrity issues.
• Collaborate with SI/PI engineers to define and meet signal and power integrity requirements.
• Optimize CoWoS-style interposer/substrate designs for electrical and thermal performance.
• Perform DRC and LVS layout verification and resolve rule violations.
• Coordinate with manufacturing teams to ensure design feasibility and yield-aware layouts.
• Maintain design documentation, guidelines, and formal handoffs to downstream teams.
• Provide technical guidance and mentorship to junior engineers.

Requirements

Must-have technical skills and experience for this role:

• 10+ years of IC substrate/package layout design experience for high-performance processors or accelerators.
• Hands-on experience with large, high-density substrate layouts and constraint-driven routing.
• Proven experience designing robust power delivery networks for high-power packages.
• Expertise in high-speed layout techniques and practical application of SI/PI at the package level.
• Advanced proficiency with Allegro Package Designer, including constraint management, routing, and verification.
• Experience with DRC/LVS and layout verification flows.
• Strong collaboration and communication skills across chip, packaging, SI/PI, and manufacturing teams.
• Strong analytical and problem-solving abilities in fast-paced engineering environments.

Nice-to-have:

• Experience optimizing thermal performance of substrates and interposers.
• Deep hands-on experience with CoWoS or similar chip-on-wafer-on-substrate assemblies.
• Scripting or automation experience for layout flows and rule checking.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field preferred. The posting also indicates equivalent practical industry experience is acceptable.

About the Company

Company: Etched

Headquarters: San Jose, CA, United States

Etched develops purpose-built AI inference ASICs and systems optimized for transformer models, aiming to deliver significantly higher performance, lower cost, and lower latency than GPUs. The company focuses on enabling applications like real-time video generation and advanced reasoning agents, and is backed by leading investors and engineers.