Standard Cell Design Engineer

Job Title

Standard Cell Design Engineer

Role Summary

Design, develop and characterize standard-cell libraries for deep-submicron, FinFET and SOI technologies. Work within foundry PDKs and design flows to deliver robust cell libraries and characterization views used by chip teams.

Role involves circuit design, device-physics awareness, characterization methodology and cross-functional collaboration with CAD, PDK and test teams.

Experience Level

Mid-level — typically 3–5 years of relevant industry experience in standard-cell library development. Candidates with a PhD and ~6 years' experience are also considered.

Responsibilities

Primary responsibilities include development, characterization and improvement of standard-cell IP and related methodologies.

• Define and modify standard-cell architecture across technologies and integrate changes into design flows.
• Design and optimize cell circuits accounting for deep-submicron device non-idealities.
• Develop and execute characterization (NLDM, CCS, ECSM views) and validate characterization results.
• Implement and improve characterization methodology and industry-standard flow automation.
• Troubleshoot and debug circuit behavior and chip-level scenarios; work with cross-functional teams to resolve issues.
• Propose and implement innovative solutions aligned with business and product requirements.
• Document results and communicate technical findings clearly in English to multi-disciplinary teams.

Requirements

Expectations are listed as must-have items and useful additions.

• Must-have: 3–5 years of experience in digital standard-cell library development and characterization for deep-submicron technologies.
• Must-have: Practical experience generating and validating characterization views (NLDM, CCS, ECSM) using industry-standard tools.
• Must-have: Strong analytical and circuit-debugging skills and ability to work in a project-driven industrial development environment.
• Must-have: Good communication and teamwork skills; able to work in a multi-cultural environment.
• Nice-to-have: Exposure to chip-level scenarios and PDK/flow methodology development.
• Nice-to-have: Scripting experience (Perl, Tcl, Python) to support automation of characterization and flows.
• Nice-to-have: Familiarity with FinFET and SOI technology specifics.

Education Requirements

MS / M.Tech in Electrical or Electronics Engineering is specified as common for this role (with 3–5 years' experience). PhD in Electronics / Electrical / VLSI is noted for candidates with ~6 years' relevant experience. No other certifications were specified.

About the Company

Company: GlobalFoundries

Headquarters: Saratoga Springs, New York, USA

GlobalFoundries is a leading contract manufacturer for the global semiconductor industry, with facilities in multiple countries, including the USA. The company develops a broad portfolio of semiconductor technologies and employs around 13,000 people worldwide. GlobalFoundries focuses on enhancing competitiveness in specialized application solutions and fostering innovation in mobile communications, consumer electronics, and automotive applications.