Staff Verification Design Engineer

Job Title

Staff Verification Design Engineer

Role Summary

Responsible for block- and chip-level verification of digital and analog/mixed-signal ASICs. Works with design teams to define verification strategy, implement test environments, run regressions and coverage, and ensure tape-out quality.

Provides post-silicon bring-up and debug support and improves verification scalability through environment and tool automation.

Experience Level

Senior; the posting requests at least 3+ years of experience in the semiconductor industry.

Responsibilities

Core responsibilities include planning and executing verification activities across RTL, gate-level and AMS domains.

• Perform block- and chip-level verification in RTL, gate-level and analog/mixed-signal (AMS) domains.
• Run digital and mixed-signal simulations and apply formal verification where appropriate.
• Collaborate with design teams to create verification strategy and detailed plans.
• Develop tests, run regressions and monitor coverage to meet tape-out quality targets.
• Participate in design and project reviews, providing verification perspective and schedule/priority assessment.
• Support post-silicon bring-up and debug for bench validation and automated test equipment (ATE) testing.
• Improve verification scalability and portability by enhancing environments and automating tools and flows.

Requirements

Must-have technical skills and attributes required for the role; nice-to-have items listed separately.

• Hands-on experience with SystemVerilog as a verification language and UVM implementation.
• Proven ability to debug digital simulations in RTL and gate-level netlists at module and system level.
• Scripting experience in Python or Perl for automation and flow integration.
• Clear understanding of the ASIC design and verification flow.
• Strong analytical, synthesis and problem-solving skills; self-motivated and able to work independently and in teams.
• Excellent verbal and written communication skills.

Nice-to-have:

• Experience setting up UVM verification environments from scratch.
• Familiarity with VHDL or SystemVerilog RNM.
• Experience automating verification flows in an industrial setting using Python/Perl.
• Analog behavioral model development and verification experience.

Education Requirements

Master's degree (M.S.) in Electrical Engineering, Computer Engineering or Computer Science or higher.

About the Company

Company: Semtech

Headquarters: Camarillo, California, USA

Semtech Corporation is a high-performance semiconductor company providing IoT systems and Cloud connectivity solutions. The company focuses on delivering innovative technology solutions that support a smarter, more connected, and sustainable planet, with a dedication to quality across infrastructure, industrial, and consumer markets.