Senior FPGA Engineer

Job Title

Senior FPGA Engineer

Role Summary

Design and implement control logic state machines and DSP algorithms in FPGA fabric for high-throughput systems. Work with cross-functional hardware, firmware, verification and validation teams to deliver products from specification through prototype to production.

Experience Level

Senior — typically 5+ years of relevant FPGA or digital design experience.

Responsibilities

Deliver RTL and FPGA implementations, perform simulation and in-circuit debug, and lead project teams to meet schedules.

• Implement control logic state machines and DSP algorithms in FPGA fabric for high-throughput systems.
• Develop RTL in Verilog and SystemVerilog and create micro-architecture from high-level specifications.
• Perform functional simulation using ModelSim or similar tools.
• Execute FPGA design flow: synthesis, place & route, pin assignments, resource fixing and partitioning.
• Target Intel (Altera) or Xilinx FPGAs using Quartus Prime or Vivado.
• Create and parameterize reusable IP blocks.
• Debug designs in-circuit using tools such as ChipScope/SignalTap and lab oscilloscopes/protocol analyzers.
• Perform static timing analysis and manage timing closure using SDC.
• Collaborate with PCB designers, firmware and application engineers, and verification/validation teams.
• Lead project teams to successful completion within deadlines and troubleshoot complex issues.

Requirements

Must-have technical skills and experience:

• Strong knowledge of digital design and multiple clock domain handling.
• Proficient in RTL design using Verilog and SystemVerilog.
• Experience creating micro-architecture from specifications.
• Experience with functional simulation (ModelSim or equivalent).
• Hands-on FPGA design and synthesis experience (map & route, pin/attribute assignments, partitioning).
• Experience targeting Intel/Altera or Xilinx devices using Quartus Prime or Vivado.
• IP creation and parametrization experience.
• In-circuit debug experience with ChipScope/SignalTap and lab instruments.
• Practical knowledge of static timing analysis and timing closure using SDC.
• Proven ability to work with cross-functional global teams and to lead projects.

Nice-to-have:

• TCL scripting and Python for build/automation and toolflow tasks.
• Experience with transceivers and PHY design.
• Power and resource utilization estimation experience.
• Experience with soft-processor cores (MicroBlaze, Nios-II).
• Familiarity with digital signal processing concepts and MATLAB/Python for algorithm design.
• Embedded systems experience in C/C++ and firmware integration.

Education Requirements

Not specified.

About the Company

Company: A&W Engineering Works

Headquarters: Sunnyvale, CA, USA

A&W Engineering Works develops and deploys end-to-end engineering solutions from front-end sensors to back-end applications, covering analog and digital signal processing, algorithms, hardware, software, mechanical design, rapid prototyping, and paths to production for complex real-world problems.