Staff Verification Design Engineer

Job Title

Staff Verification Design Engineer

Role Summary

Responsible for planning and executing RTL, gate-level and mixed-signal verification for ASIC blocks and full-chip designs. Works with design teams to define verification strategy, implement verification environments, run regressions, and support post-silicon bring-up.

Experience Level

Senior — role expects experienced engineers; posting specifies a minimum of 3+ years in the semiconductor industry.

Responsibilities

Primary verification responsibilities include simulation, formal checks, coverage-driven testing, and post-silicon debug.

• Develop verification strategy and detailed verification plans for blocks and full chips.
• Implement UVM/SystemVerilog testbenches, develop tests, and maintain regression suites.
• Run RTL, gate-level and analog/mixed-signal simulations; perform formal verification where applicable.
• Monitor coverage metrics and drive issues to tape-out quality.
• Participate in design and project reviews from a verification perspective and advise on schedule/priorities.
• Support post-silicon bring-up and debug for bench validation and ATE testing.
• Improve verification scalability and portability through environment enhancements and automation.

Requirements

Must-have technical skills and experience.

• 3+ years of experience in the semiconductor industry.
• Hands-on experience with SystemVerilog as a verification language and practical UVM implementation experience.
• Experience debugging digital simulations at RTL and gate-level, isolating module- and system-level issues.
• Scripting experience in Python or Perl for test and flow automation.
• Clear understanding of the ASIC design and verification flow.
• Strong analytical, problem-solving, and synthesis skills.
• Effective verbal and written communication; able to work independently and in teams.

Nice-to-have:

• Experience setting up UVM verification environments from scratch.
• Familiarity with VHDL or SystemVerilog RNM.
• Experience automating verification flows in an industrial setting with Python/Perl.
• Analog behavioral model development or mixed-signal verification experience.

Education Requirements

M.S. in Electrical Engineering, Computer Engineering, Computer Science, or higher degree is specified. No alternative "equivalent experience" degree language provided in the source.

About the Company

Company: Semtech

Headquarters: Camarillo, California, USA

Semtech Corporation is a high-performance semiconductor company providing IoT systems and Cloud connectivity solutions. The company focuses on delivering innovative technology solutions that support a smarter, more connected, and sustainable planet, with a dedication to quality across infrastructure, industrial, and consumer markets.