Staff Verification Applications Engineer

Job Title

Staff Verification Applications Engineer

Role Summary

Work with customers to deploy and scale VCS simulation and Verdi debug tooling into real verification flows for complex SoC designs. Act as the technical lead on customer integrations, problem reproduction, and flow automation while feeding deployment insights back to R&D and product teams.

Primary interactions are with customer design and verification teams, product validation, and global R&D to ensure verification flows meet tape-out requirements.

Experience Level

Senior-level. The posting indicates a typical experience range of 5–12 years in verification or applications engineering.

Responsibilities

Key responsibilities include hands-on deployment, debugging, and automation to make simulation and debug tools operational at customer scale.

• Deploy VCS and Verdi into customer verification flows and integrate with existing toolchains.
• Diagnose and resolve complex issues across UVM testbenches, SVA assertions, Low Power (UPF) flows, and Gate Level Timing simulations.
• Reproduce customer issues, develop testcases or scripts that demonstrate root cause, and coordinate fixes with R&D.
• Lead competitive benchmarks and performance/debug efficiency evaluations for customers.
• Develop and maintain automation and flow scripts (Perl, Tcl, Python, Shell, Make) to improve productivity.
• Interface with customers, product validation, and R&D to propose solutions and close deployment loops.
• Support adoption of AI-driven verification productivity features and advanced simulation capabilities.

Requirements

Must-have technical skills and experience; a short list of desirable extras follows.

• Must-have: Strong working knowledge of VCS simulation technology and Verdi debug platform or equivalent simulation/waveform debug tools.
• Must-have: Deep expertise in SystemVerilog, UVM, SVA, and verification methodologies applied to real RTL designs.
• Must-have: Proven experience with Low Power (UPF) flows and Gate Level Timing simulations in customer or validation contexts.
• Must-have: Advanced scripting skills (Perl, Tcl, Python, Shell, Make) for automation and flow development.
• Must-have: Solid digital design fundamentals, familiarity with Verilog/VHDL and UNIX/Linux environments; strong debugging and customer-facing troubleshooting skills.
• Must-have: Ability to manage multiple customer engagements across time zones and travel for onsite customer work when needed.
• Nice-to-have: Exposure to DPI, C/C++, SystemC, Functional Safety, or GenAI technologies.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering or a related field is specified. The posting indicates 5–12 years of hands-on verification or applications engineering experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.