Staff Technical Program Manager, ASIC

Job Title

Staff Technical Program Manager, ASIC

Role Summary

Lead the end-to-end Electronic IC (EIC) ASIC program from specification through tapeout, post-silicon bring-up, and system integration. Serve as the single source of truth for schedule, risk, and readiness while coordinating architecture, design, verification, physical design, packaging, photonics, and external partners.

Implement and scale AI-augmented program tooling and processes to accelerate development and verification.

Experience Level

Senior-level - typically 10+ years of ASIC/SoC program experience, with multiple silicon programs taken from architecture through tapeout and post-silicon bring-up.

Responsibilities

Drive technical program execution and cross-functional coordination for a first-silicon mixed-signal ASIC project.

• Maintain integrated schedule, milestones, dependency map, staffing outlook, and risk register from architecture through production readiness.
• Lead specification convergence, design reviews, freeze criteria, decision logs, and change control with architecture and design teams.
• Coordinate RTL, DV, analog/mixed-signal, DFT, physical design, packaging, firmware, and software efforts and external partners (foundry, IP vendors, OSAT, EDA).
• Manage foundry engagement, PDK/deck updates, shuttle/full-mask schedules, wafer starts, and mask release logistics.
• Build and run tapeout readiness checklist and decision process (verification closure, timing/physical/electrical signoff, DRC/LVS, mask release).
• Plan and execute post-tapeout bring-up: lab readiness, package/OSAT coordination, ATE and bench tests, silicon debug triage, errata tracking, and respin scoping.
• Track cross-domain dependencies with photonic IC, package/substrate, board, firmware, and software teams; surface risks early and drive mitigations.
• Run program rhythm: cross-functional syncs, phase-gate reviews (PDR/CDR/tapeout/bring-up), escalation paths, and executive reporting.

Requirements

Must-have technical program management experience and operational skills for complex silicon programs.

• 10+ years leading ASIC/SoC development programs in a TPM/EPM or equivalent lead role.
• At least 2 complete silicon programs taken from architecture/specification through tapeout, with post-silicon bring-up and system integration experience.
• Practical knowledge across the silicon lifecycle: architecture, front-end, verification, FPGA/emulation, physical design, DFT, signoff, packaging, foundry processes, bring-up, ATE, and qualification.
• Experience managing foundry, IP vendor, OSAT, and design-services relationships and tapeout logistics.
• Strong technical breadth to evaluate schedules, assess technical risks, and communicate credibly with engineering teams.
• Proven cross-functional leadership aligning multiple teams and external partners without direct authority.
• Hands-on with program tooling (Jira or equivalent), dependency/schedule tracking, dashboards, and checklists.
• Daily use of AI tools in program work and an automate-first instinct with appropriate human verification judgment.
• Nice-to-have: mixed-signal/high-speed analog, optical transceivers/silicon photonics exposure, advanced packaging (2.5D/3D), prior hands-on design/DV/physical-design background, or TPM experience on ML accelerator/data-center hardware programs.

Education Requirements

BS in Electrical or Computer Engineering (or equivalent). MS preferred. Equivalent practical experience accepted.

About the Company

Company: Neurophos

Headquarters: Sunnyvale, California, United States

Startup developing silicon-photonic AI accelerator chips that use programmable metasurfaces and dense optical cells to perform matrix multiplications at the speed of light, targeting large-scale AI inference with much higher energy efficiency and performance than traditional electronic approaches.