Staff STA Engineer

Job Title

Staff STA Engineer

Role Summary

Lead static timing analysis (STA) and timing-closure activities for advanced silicon demonstrator projects using 5nm/3nm process technology and modern SoC integration (2.5D/3D). Work within a cross-functional silicon engineering team to ensure functional and test-mode timing across blocks and full-chip topologies.

Experience Level

Senior — requires significant hands-on STA and timing-closure experience; the posting specifies 6+ years of relevant industry experience.

Responsibilities

Primary responsibilities include defining and driving timing closure across hierarchical levels, coordinating ECOs, and resolving complex timing issues with multiple teams and vendors.

• Own full-chip and block-level static timing closure throughout the project lifecycle for complex multi-instantiated designs.
• Develop and maintain timing constraints for functional and test modes at various logical hierarchy levels.
• Diagnose and resolve sophisticated timing issues in major SoC building blocks, coordinating with design, verification, physical implementation, and EDA vendors.
• Generate and manage ECOs at block and top level and coordinate their implementation with relevant teams.
• Work with multi-power-domain designs and account for timing corners, process variation, DFT/test modes, and signal integrity effects.
• Interface with IO and on-chip bus protocols as required for timing closure across interfaces.

Requirements

Must-have technical skills and experience; a short list of preferred additions is included after must-haves.

• 6+ years of industry experience in timing convergence and STA.
• Hands-on experience with industry-standard STA tools and methodologies.
• Knowledge of timing corners/modes, process variation, DFT/test impacts, and signal integrity considerations.
• Experience achieving timing closure on multi-power-domain SoC designs.
• Proven collaboration with internal silicon engineering teams and EDA vendors.
• Direct experience with constraints development and timing closure on advanced nodes (5nm or 3nm).
• Strong automation skills (Perl, Tcl, Python or equivalent) to create flows and analysis scripts.

Nice-to-have:

• Familiarity with synthesis, logic equivalence checking, DFT, CLP, and backend methodologies and tools.
• Additional coding experience in Perl/Python/TCL or similar scripting languages.
• Strong presentation and cross-team communication skills.

Education Requirements

Master's degree in Electrical Engineering or equivalent experience is listed as a nice-to-have. The posting allows equivalent practical experience in place of the degree.

About the Company

Company: Arm

Headquarters: Cambridge, United Kingdom

ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.