Staff / Sr. Staff System FPGA Engineer

Job Title

Staff / Sr. Staff System FPGA Engineer

Role Summary

Individual contributor on the platform systems engineering team responsible for implementing FPGA architectures for control-plane and telemetry on server reference platforms based on Qualcomm Snapdragon SoCs.

Work closely with SoC, firmware, hardware, software, and suppliers to deliver RTL, verification, lab bring-up, and integration for system reference designs.

Experience Level

Senior-level role. Typical background: 5+ years in FPGA implementation and verification; 10+ years preferred for Sr. Staff expectations. Minimum qualifications allow reduced years with advanced degrees.

Responsibilities

Key day-to-day responsibilities include:

• Translate system architecture specifications into synthesizable RTL (Verilog/SystemVerilog).
• Develop and run verification environments and test benches; automate regression flows.
• Perform synthesis, place-and-route, timing closure, and write timing constraints.
• Bring up FPGA hardware in the lab; debug with JTAG, logic analyzers, and scopes.
• Author and maintain technical documentation, test results, and known issues.
• Create Python-based scripts and cocotb test benches for automation and verification.
• Use git/GitHub workflows for source control, code reviews, and CI integration.
• Collaborate with cross-functional teams during system integration and supplier/customer engagements; travel as required.

Requirements

Must-have skills and experience (concise):

• 5+ years hands-on FPGA implementation and verification experience.
• Proficiency in Verilog and/or SystemVerilog: simulation, test bench creation, synthesis, and debugging.
• Strong Python scripting skills for automation, test infrastructure, and tooling.
• Experience with cocotb for Python-based RTL verification.
• Practical experience with FPGA vendor toolchains and hardware bring-up.
• Familiarity with common interfaces and protocols such as AXI4, PCIe, DDR5, I2C, UART (experience with high-speed SerDes, PCIe 5/6, DDR5/LPDDR5X is preferred).
• Working knowledge of git and GitHub, including CI/CD and code review practices.
• Strong debugging, problem reporting, and written/verbal communication skills.

Preferred / nice-to-have:

• Experience authoring XDC/SDC constraints and performing timing closure on multi-clock designs.
• Clock domain crossing techniques, CDC analysis, SVA, and functional coverage methodologies.
• Embedded soft-core processor integration (e.g., MicroBlaze, NIOS II, RISC-V) and server management standards (IPMI, MCTP, PLDM, OpenBMC).
• Familiarity with vendor-specific flows (AMD/Xilinx Vivado/Vitis or Intel/Altera Quartus) and CI-driven simulation/regression flows.
• Comfort using AI-assisted engineering tools to improve productivity.

Education Requirements

Bachelor's, Master's, or PhD in Engineering, Computer Science, Information Systems, or a related technical field are cited. Minimum-qualification alternatives: Bachelor's +4 years relevant experience, Master's +3 years, or PhD +2 years. Equivalent practical experience is accepted per those minimums.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.