Staff/Sr Staff Engineer, Physical Design

Job Title

Staff/Sr Staff Engineer, Physical Design

Role Summary

Lead block- and subsystem-level physical implementation and closure for complex hierarchical SoCs at advanced process nodes. Focus areas include timing closure, congestion mitigation, power integrity, and clocking integration.

The role collaborates closely with SoC-level teams (clocking, floorplanning, STA, power, verification, backend) to align subsystem implementation with overall SoC strategies; it does not own SoC-level execution.

Experience Level

Senior - typically 10+ years of experience in physical design with demonstrated subsystem-level closure for complex SoCs.

Responsibilities

Primary responsibilities include delivering high-quality subsystem physical closure and improving methodologies and automation.

• Lead block- and subsystem-level timing closure, congestion mitigation, and physical implementation quality efforts.
• Coordinate with SoC-level physical design teams to align on clocking strategy, floorplan intent, and integration requirements.
• Apply and validate clocking methodologies to ensure subsystem clock domains integrate into the SoC clock architecture.
• Develop, refine, and scale closure methodologies, flows, and automation to improve predictability and execution efficiency.
• Mentor and guide physical design engineers on best practices, methodology adoption, and technical rigor.
• Work cross-functionally with RTL design, STA, power, verification, and backend teams to ensure smooth handoffs and robust closure.
• Proactively identify, assess, and mitigate physical design risks; coordinate with SoC teams to drive resolutions.

Requirements

Must-have technical skills, tools, and experience for successful execution at subsystem level.

• Extensive experience in timing closure and constraint management at block and subsystem level.
• Expertise in congestion analysis and resolution.
• Strong knowledge of power integrity and power-aware physical implementation techniques.
• Deep understanding of clock domain partitioning, clock tree architecture, skew management, and clock gating (subsystem-level integration focus).
• Hands-on with industry tools such as Synopsys ICC2, Fusion Compiler, PrimeTime and Cadence Innovus, Tempus, Certus, and related signoff/analysis platforms.
• Proficiency in scripting and automation (Tcl, Python, and/or Perl).
• Familiarity with end-to-end SoC flows and strong cross-team collaboration (timing, power, clocking, verification, backend).
• Experience with low-power design techniques and power-aware implementation methodologies.

Education Requirements

B.Tech or M.Tech in Electronics & Communication, Electrical Engineering, Computer Science, or a related technical field.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.