Staff / Sr. Staff Engineer DV
Lead verification of low-power RISC‑V CPU designs, focusing on power-aware methodologies and UPF flows. Work closely with microarchitecture and RTL teams to achieve quality closure at CPU and block levels.
Provide technical leadership, mentor junior engineers, and participate in test planning and execution for new architecture and design features.
Senior-level — typically 7+ years of relevant experience in low-power verification, power-aware design, or power management.
Primary responsibilities include verification ownership, driving quality closure, cross-team collaboration, and mentoring.
Must-have technical skills and experience. Nice-to-have items noted.
Bachelor's or Master's degree in Electrical & Electronic Engineering, Electrical & Communication Engineering, VLSI, or equivalent practical experience.
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
