Interconnect Design Engineer

Job Title

Interconnect Design Engineer

Role Summary

Staff-level hardware engineer responsible for architecting and implementing TileLink interconnects, cache controllers, protocol bridges, and related uncore IP. Work involves developing highly-configurable RTL generators using Chisel/FIRRTL, integrating with verification and tooling, and improving performance and coherence for multi-core systems.

Role is cross-functional and collaborative, contributing design, verification coordination, and documentation to move configurable hardware IP to market quickly and reliably.

Experience Level

Senior (staff-level). Specific years of experience not stated.

Responsibilities

Primary responsibilities include design, integration, verification support, and documentation of interconnect and uncore IP.

• Architect, design and implement TileLink interconnects, cache controllers, protocol bridges, and other infrastructure logic as RTL generators in Chisel.
• Implement RTL generators that self-configure to optimally connect to each other.
• Enhance designs for higher performance and more efficient multi-core/multi-system coherence.
• Design extensive configurability as a first-class consideration.
• Integrate new design content into the Chisel/FIRRTL framework and improve tooling for automatic configuration, documentation, verification testbenches, and packaged software.
• Perform initial sandbox verification and collaborate with verification teams to create and execute thorough verification plans.
• Create and maintain design documentation and share knowledge across the team.

Requirements

Must-have technical skills and competencies.

• Knowledge of cache and cache coherency architectures and concepts.
• Experience with NoC or other interconnect fabrics and with industry-standard bus protocols (AXI, AHB, APB, CHI).
• Ability to architect solutions connecting bus fabrics with disparate protocols.
• Strong software engineering background: functional and object-oriented programming, templated metaprogramming, and test-driven development.
• Familiarity with compiler infrastructures, domain-specific languages, and intermediate representations for optimization/transformation.
• Proficiency in RTL design using Verilog, SystemVerilog, or VHDL.
• Attention to detail, focus on high-quality design, and effective teamwork skills.

Nice to have

• Experience with Scala/Chisel, Bluespec, or other DSLs for configurable hardware.
• Knowledge of RISC-V architecture.
• Experience with Git/GitHub, Jira, Confluence.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline, or equivalent practical experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.