Principal Interconnect Design Engineer

Job Title

Principal Interconnect Design Engineer

Role Summary

Principal engineer responsible for architecting and implementing high-performance interconnect IP, cache controllers, protocol bridges and related uncore infrastructure as configurable RTL generators. The role works within a hardware-IP team that develops CPU and interconnect IP using Chisel and the FIRRTL toolchain to deliver configurable, production-quality IP for SoC designs.

Work includes design, integration into the Chisel/FIRRTL framework, verification planning and producing documentation to enable reuse across products.

Experience Level

Senior / Principal-level. The posting does not specify a required number of years of experience.

Responsibilities

Core responsibilities include design, integration, verification, and documentation of interconnect and uncore IP.

• Architect, design and implement enhanced TileLink interconnects, cache controllers, protocol bridges, and other uncore logic as RTL generators in Chisel.
• Implement RTL generators so elements self-configure to optimally connect with each other.
• Improve designs for higher performance and more efficient multi-core and multi-system coherence.
• Design extensive configurability into IP as a first-class consideration.
• Integrate new designs into the Chisel/FIRRTL framework and contribute framework improvements to enable automatic generation of documentation, verification testbenches, tests, and packaged software.
• Perform initial sandbox verification and collaborate with the design verification team to create and execute thorough verification plans.
• Create and maintain clear design documentation and participate in collaborative design reviews.

Requirements

Must-have technical skills and attributes; education specifics are listed separately below.

• Strong knowledge of cache and cache-coherency architectures and concepts.
• Experience with NoC or other interconnect fabrics.
• Familiarity with industry-standard bus/protocols (AXI, AHB, APB, CHI, CXL, UCIe) and ability to architect protocol bridges.
• Strong software engineering background: object-oriented and functional programming, templated metaprogramming, compiler/DSL infrastructure, data modeling for IRs, and test-driven development.
• Proficiency in RTL design using Verilog, SystemVerilog, or VHDL.
• Attention to detail and commitment to high-quality design and verification practices.
• Effective collaboration and communication skills; able to work in cross-functional teams.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline — or equivalent practical experience.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.