Staff SoC Physical Verification Engineer, HBM

Job Title

Staff SoC Physical Verification Engineer, HBM

Role Summary

Senior physical verification engineer responsible for end-to-end sign-off of full-chip and hierarchical advanced-node SoC and HBM logic die designs. The role sits in the Heterogeneous Integration Group and interfaces with physical design, EDA, foundry, and product teams to achieve tape-out quality under schedule and reliability constraints.

Primary focus areas: DRC, LVS, ERC/PERC, reliability checks, DFM, sign-off flows, and tooling/automation for advanced process nodes.

Experience Level

Senior — preferred 10+ years of relevant industry experience; significant hands-on experience with advanced-node full-chip or block-level physical verification.

Responsibilities

Accountable for physical verification sign-off, verification flow development, and cross-functional closure for advanced SoC designs.

• Lead end-to-end physical verification sign-off for full-chip and hierarchical designs (DRC, LVS, ERC, PERC, antenna checks, DFM).
• Execute, debug, and customize foundry rule decks and manage waiver processes to drive clean closure.
• Perform reliability verification across power domains (ESD, latch-up, electromigration, floating nets, connectivity).
• Run density, metal fill, and CMP checks to ensure manufacturability at 3nm and below.
• Perform parasitic RC extraction and support correlation between verification results and post-silicon measurements.
• Develop and maintain verification automation, regression infrastructure, and sign-off flows using Python, Tcl, Perl, or similar.
• Drive adoption of ML/AI-based verification and PPA optimization tools.
• Partner with physical design, custom layout, CAD, RTL, product engineering, EDA, and foundry teams (including direct foundry interface) from kick-off through tape-out readiness.

Requirements

Must-have technical skills and experience for successful performance in the role. Education items are summarized in the Education Requirements section below.

Must-have:

• Proven experience with full-chip or block-level physical verification for advanced-node SoC, memory, or heterogeneous integration designs.
• Deep hands-on expertise in physical verification methodologies (DRC, LVS, ERC, PERC, DFM, antenna, reliability sign-off).
• Experience with industry physical verification tools such as Calibre, IC Validator (ICV), Pegasus, or similar, including rule deck development or customization.
• Working knowledge of RTL-to-GDS implementation flows (place-and-route, extraction) and their impact on verification outcomes.
• Strong scripting and automation skills (Python, Tcl, Perl, or similar) to develop flows and regression infrastructure.
• Ability to drive verification closure via clear cross-functional communication in a global engineering environment.

Nice-to-have:

• Experience with HBM, DRAM, multi-die/chiplet, or 2.5D/3D integration verification.
• Background in GPU/CPU/high-performance accelerator implementation at advanced nodes and familiarity with foundry DRC/BEOL/FEOL rules and DFM best practices.
• Exposure to post-silicon failure analysis, yield learning, or layout-based debug correlated with silicon behavior.

Education Requirements

Preferred: Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience. The posting also references a preference for candidates with 10+ years of relevant industry experience. (No exclusive requirement for a specific degree was stated — equivalent practical experience is acceptable.)

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.