Staff SoC Layout/EDA Designer

Job Title

Staff SoC Layout/EDA Designer

Role Summary

The Staff SoC Layout/EDA Designer will develop and deliver complex analog/RF/mixed-signal block layouts and chip-level SoC macros from concept through tape-out and production. You will work on floorplanning, verification/debug, layout automation, and collaborate across global analog, digital and verification teams.

Experience Level

Senior — requires experienced engineer. The role expects at least 5+ years of relevant industry experience.

Responsibilities

Primary responsibilities include design, automation, verification and team leadership for SoC layout.

• Create and optimize layouts of complex analog/RF/mixed-signal blocks and chip-level SoC macros.
• Own block-level layouts and top-level floorplanning, including hierarchical verification and debug.
• Develop and maintain automated/custom layout flows and scripts; support batch-mode operations.
• Produce layouts following industry best practices and physical verification requirements.
• Document and communicate layout flows, participate in design reviews and manage tape-out processes and project archives.
• Manage or support layout contractors and mentor junior layout designers.
• Collaborate with global cross-functional teams to ensure specification compliance and on-time delivery.
• Work independently on complex tasks while coordinating with the broader team.

Requirements

Must-have technical skills, constraints, and experience. Education items are summarized under Education Requirements below.

• Minimum 5+ years relevant industry experience in analog/RF/mixed-signal layout for SoC development.
• Strong hands-on experience with Cadence Virtuoso and PDK layout tools (OA, CDL, GDS).
• Experience with physical verification tools and flows (Pegasus/Calibre; DRC, LVS, ERC, PERC, LVL).
• Detailed experience with deep sub-micron CMOS nodes (40 nm and below).
• Understanding of layout-dependent effects, antenna/ESD issues, isolation techniques, matching, PnR parasitics, and EMIR concepts.
• Familiarity with digital physical-design formats and flows (VHDL/Verilog, LEF/DEF) and integration with digital teams.
• Scripting proficiency (Linux shell, Makefile, Modules, SKILL, TCL, Python) and experience with automation or LLM clients is desirable.
• This position is not eligible for visa sponsorship by the company.

Education Requirements

Minimum: Associate's degree in Electronic Engineering or related field. Bachelor's degree in Electrical/Electronic Engineering, Computer Engineering, Computer Science or related technical discipline is preferred.

About the Company

Company: Qorvo

Headquarters: Greensboro, NC, US

Qorvo supplies innovative semiconductor solutions that enhance connectivity and power for a variety of applications, including consumer electronics, automotive, and healthcare. With a focus on RF and power solutions, Qorvo combines technology leadership and global manufacturing to address complex challenges in fast-growing industries. Their commitment to excellence and innovation drives them to shape the future of wireless communications.