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Staff SoC DFT Engineer, HBM

Micron Technology
August 19, 2026
Full-time
On-site
Folsom, California, United States
$146,000 - $247,000 USD yearly
DFT Jobs, Level - Senior

Job Title

Staff SoC DFT Engineer, HBM

Role Summary

Design and deliver system-on-chip (SoC) Design-for-Test (DFT) solutions for High Bandwidth Memory (HBM) base-die SoCs in Micron's Heterogeneous Integration Group. Work across RTL, implementation, verification, and manufacturing teams to ensure testability, manufacturability, and successful silicon bring-up.

Experience Level

Senior β€” 7+ years of relevant experience in SoC design, DFT, or ASIC/SoC implementation.

Responsibilities

Key responsibilities include architecture, implementation, and sign-off of SoC-level DFT for HBM base-die designs.

  • Own SoC-level DFT architecture and implementation: scan, MBIST, LBIST (where applicable), JTAG/boundary scan, and test access architectures.
  • Define DFT architecture early and align with integration, floorplanning, timing, power, and physical design.
  • Implement and integrate DFT logic at block, subsystem, and full-chip levels; collaborate with RTL and SoC integration teams.
  • Complete and sign off DFT flows, including linting, CDC checks, DFT rule checks, ATPG readiness, and coverage closure.
  • Collaborate with physical design to optimize placement, routing, timing closure, and DRC/LVS signoff.
  • Work with verification, product engineering, test, probe, and manufacturing to ensure testability, diagnosability, and efficient postsilicon bring-up.
  • Partner with CAD and methodology teams to standardize/improve DFT flows and mentor engineers.

Requirements

Must-have technical skills and experience:

  • Hands-on experience in SoC DFT architecture and implementation, including scan insertion, MBIST/LBIST concepts, boundary scan, and ATPG.
  • Experience across full RTL-to-GDS flows and collaboration with synthesis, STA, and physical design teams.
  • Proficiency with industry EDA tools for DFT and implementation (examples: Synopsys, Cadence, Siemens).
  • Experience collaborating with physical design, verification, and manufacturing teams to ensure testability and bring-up.

Nice-to-have:

  • Experience with large, complex SoCs integrating multiple IP blocks and subsystems.
  • Strong RTL debugging and design-analysis skills.
  • Scripting skills for flow automation (Python, Tcl, Perl).
  • Familiarity with memory systems (DRAM, HBM) and JEDEC specifications.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.


About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.

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Date Posted: 2026-08-19