Principal Package Design Engineer

Job Title

Principal Package Design Engineer

Role Summary

Lead design, development, and qualification of advanced semiconductor packaging solutions and drive cross-functional integration from concept through high-volume production. The role partners with IC design, applications, manufacturing, suppliers (OSATs), and quality teams to deliver reliable, manufacturable package architectures for high-performance and power semiconductor products.

Focus areas include package architecture, thermal/mechanical/electrical simulation, assembly and qualification processes, and supplier strategy. Occasional travel to suppliers or manufacturing sites may be required.

Experience Level

Senior — Principal level. Typical guidance: 5+ years of experience in advanced semiconductor or electronics packaging; proven technical leadership in package development and qualification.

Responsibilities

Core responsibilities include taking technical ownership for package solutions and ensuring manufacturability and reliability across product life cycle.

• Lead design, development, and qualification of advanced packaging (flip‑chip, WLP/FOWLP, panel‑level, 2.5D/3D, SiP, BGA/CSP, W2W/D2W heterogeneous bonding).
• Define package architecture and perform electrical, thermal, mechanical, and reliability tradeoffs and simulations.
• Drive OSAT and vendor selection, NPI readiness, and assembly/process development with suppliers and manufacturing partners.
• Oversee layout, stack‑up, material selection, interconnect strategy, and design‑for‑manufacturability (DFM) decisions.
• Plan and lead qualification activities: DOE planning, failure analysis, reliability testing, and corrective actions.
• Troubleshoot yield and packaging issues during prototyping, qualification, and production ramp; implement process improvements.
• Create and maintain package specifications, design rules, process documentation, and technical reports; mentor junior engineers.

Requirements

Must-have technical skills and experience to perform the role.

• 5+ years of hands-on experience in advanced semiconductor or electronics packaging (experience requirement retained here as role guidance).
• Deep, practical knowledge of packaging technologies, materials, assembly processes, and system integration for power and high-performance devices.
• Proven expertise in thermal, mechanical, and electrical simulation and modeling; strong background with CAD and simulation tools.
• Experience with package reliability testing, qualification standards, and failure analysis.
• Experience working with OSATs, substrate vendors, assembly houses, and semiconductor supply chains.
• Strong problem‑solving skills, project leadership, and cross‑functional communication.
• Preferred: hands‑on experience with package design and simulation tools (e.g., Cadence Allegro Package Designer, SolidWorks, ANSYS, COMSOL) and knowledge of JEDEC/IPC standards.

Education Requirements

Required: MSc or PhD in Electrical Engineering, Materials Science, Mechanical Engineering, Chemical Engineering, or a related technical field (per posting). Preferred qualifications also reference master's or doctoral degrees in relevant engineering disciplines.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.