Staff Silicon Photonics Engineer, Receiver (Rx)

Job Title

Staff Silicon Photonics Engineer, Receiver (Rx)

Role Summary

Lead development of the receiver (Rx) photonic integrated circuit (PIC) for the Neurophos OPU platform, owning photodetector device design through chip-level architecture, layout, tapeout, and silicon validation. Collaborate with electronic IC, optics, packaging, and test teams to optimize bandwidth, sensitivity, noise, density, and power at the system level.

Full-time onsite role based in Austin, TX or Sunnyvale, CA.

Experience Level

Senior-level. Minimum ~3 years of relevant experience required; 5+ years preferred.

Responsibilities

Accountable for defining and delivering the Rx PIC and related device-level and system-level solutions.

• Define Rx PIC architecture including optical input coupling (free-space and waveguide), routing, demultiplexing, and dense photodetector array layout against system link and power budgets.
• Design and optimize high-speed photodetectors (e.g., Ge-on-Si PIN and avalanche; waveguide-coupled and surface-normal) for responsivity, dark current, capacitance, bandwidth, linearity, and saturation.
• Model devices and receivers with optical, electrical, and RF simulation tools and develop photodetector equivalent circuits for co-design with TIAs.
• Collaborate with electronic IC team on PD–TIA interface, addressing pad/interconnect parasitics, biasing, input-referred noise, and integration approaches (flip-chip, 3D, co-packaged).
• Analyze array-level effects (optical/electrical crosstalk, uniformity, thermal behavior, yield) and define test structures and DFT features.
• Lead layout, verification, and tapeout of Rx PIC test vehicles and product blocks using foundry silicon photonics PDKs.
• Support die- and wafer-level characterization (responsivity, dark current, O/E bandwidth, sensitivity, BER) and use measurements to calibrate models and improve designs.
• Evaluate new detector materials, structures, and coupling approaches to improve receiver performance or density.

Requirements

Must-have technical skills and experience:

• Minimum ~3 years of relevant experience in high-speed silicon photonics focused on photodetectors and receiver PICs.
• Hands-on design experience with Ge-on-Si or equivalent high-speed photodetectors, including trade-offs among responsivity, bandwidth, capacitance, and dark current.
• Proficiency with photonic and device simulation tools (Lumerical/Ansys, COMSOL, Synopsys TCAD, or equivalent) and circuit-level photodetector modeling.
• Experience with layout and tapeout in silicon photonics foundry PDKs (e.g., KLayout, gdsfactory, Cadence Virtuoso, or equivalent).
• Working knowledge of optical receiver fundamentals: TIA interfacing, noise, sensitivity, and PAM4 signal integrity.
• Experience addressing PD–TIA interfacing and integration approaches (flip-chip, 3D, co-packaged).
• Experience planning and supporting die/wafer characterization and test; ability to interpret measurements to refine models and designs.

Nice-to-have:

• 5+ years developing high-speed silicon photonics receivers or photodetectors.
• Experience taking devices through full design→tapeout→fabrication→test cycle and designing large/dense photodetector arrays or free-space/surface-normal coupling.
• Experience co-designing PDs with CMOS/SiGe TIAs or working with advanced detector platforms (avalanche photodiodes, III-V/Si heterogeneous detectors); publications or patents in photodetectors/receivers.

Education Requirements

PhD in Electrical Engineering, Applied Physics, Physics, or a closely related field is specified as required.

About the Company

Company: Neurophos

Headquarters: Sunnyvale, California, United States

Startup developing silicon-photonic AI accelerator chips that use programmable metasurfaces and dense optical cells to perform matrix multiplications at the speed of light, targeting large-scale AI inference with much higher energy efficiency and performance than traditional electronic approaches.