Staff / Senior Staff / Principal Engineer, Design Verification

Job Title

Staff / Senior Staff / Principal Engineer, Design Verification

Role Summary

Lead end-to-end design verification for complex SoC digital IPs and subsystems from specification through sign-off. Develop verification strategies, build reusable UVM environments, and coordinate with RTL, architecture, emulation, and SoC verification teams to ensure integration and quality.

Mentor engineers, adopt advanced verification techniques (including AI/ML-assisted methods), and support gate-level simulation, low-power verification, and post-silicon debug as required.

Experience Level

Senior-level. Target experience: 5–15 years in SoC verification and related domains.

Responsibilities

Execute and lead verification activities to achieve robust IP/subsystem sign-off.

• Define and drive IP-level verification strategies, test plans, coverage models, and closure criteria.
• Develop scalable, reusable UVM-based verification environments for IP and subsystem verification.
• Lead functional, code, assertion, and cross-coverage closure; report clear metrics for sign-off.
• Apply AI/ML-assisted verification techniques to accelerate coverage convergence and identify stimulus gaps.
• Drive constraint-random and directed test methodologies for protocol, corner-case, and stress verification.
• Develop advanced checkers, scoreboards, SVA assertions, and protocol monitors.
• Collaborate with RTL, architecture, emulation, and SoC teams to ensure seamless IP integration.
• Work with EDA vendors to evaluate and adopt next-generation verification, coverage, and analytics tools.
• Mentor junior engineers and promote best-in-class verification practices and continuous improvement.
• Support gate-level simulation, low-power verification, and post-silicon debug when required.

Requirements

Core technical requirements and preferred skills.

• 5–15 years of experience in SoC verification domains with working knowledge of industry-standard EDA toolkits.
• Strong expertise in UVM-based testbench architecture and development.
• Deep understanding of SystemVerilog, UVM, and assertions (SVA); proficiency in Verilog/SystemVerilog.
• Experience with metric-driven verification, including functional and code coverage closure.
• Experience debugging complex design issues in simulation, emulation, and post-silicon environments.
• Proficiency in C/C++ and shell scripting for testbench and automation tasks.
• Strong analytical, problem-solving, and communication skills; experience mentoring teams.
• Preferred: hands-on experience with AI/ML-based verification tools for coverage gap analysis, test stimulus optimization, and regression triage.
• Preferred: scripting expertise in Python, Perl, or TCL; exposure to formal verification and hybrid formal-simulation flows.
• Preferred: familiarity with high-speed or complex IPs (e.g., H.264), security, debug, or safety-critical domains.

Education Requirements

Bachelor's or master's degree in Electronics Engineering.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.