Staff / Senior Staff Physical Design Engineer

Job Title

Staff / Senior Staff Physical Design Engineer

Role Summary

Lead physical implementation for complex SoC and block-level designs on advanced FinFET nodes. Define and own backend physical-design methodology, drive integration of Agentic AI into PD flows, collaborate with foundry and EDA vendors, and mentor engineers across the team.

Experience Level

Senior-level. Minimum qualifications specify Bachelor's +6 years, Master's +5 years, or PhD +4 years of ASIC design/verification/validation/integration experience. Preferred experience includes significantly more years (posting lists Master's +12+ years as preferred).

Responsibilities

Accountable for end-to-end backend physical design and for establishing team methodology and flows. Typical responsibilities include:

• Define, model, design, optimize, verify, validate and implement IP (block/SoC) physical implementation from block to chip level.
• Lead full-chip and block-level floorplanning, place-and-route, clock architecture, STA, and timing/power closure to achieve physical sign-off.
• Develop and validate advanced design rules and processes; conduct complex simulations and analyses to optimize power, performance, and area.
• Collaborate with cross-functional teams (design, verification, validation, software, architecture) to incorporate requirements and improve yield and quality.
• Evaluate and improve process flows from RTL to GDS, including synthesis, P&R, timing, power analysis and verification.
• Write and review technical documentation and present methodology, risk assessments, and tape-out readiness to senior management.

Requirements

Core technical requirements and desirable skills. Education and degree-specific experience requirements are summarized separately below.

• Must-have: Deep expertise in floorplanning, place-and-route, clock architecture, STA, timing and power closure, and physical sign-off for advanced nodes.
• Experience with power optimization techniques (DVFS, multi-Vt, power domains, UPF/CPF).
• Expert proficiency with EDA toolflows (Cadence, Synopsys, Mentor, Ansys).
• Advanced scripting skills (Shell, Python, Tcl) and ability to architect large-scale PD automation frameworks.
• Proven experience designing, implementing, and owning end-to-end backend design flows at a team or organization level.
• Strong verbal and written communication; able to present technical decisions and influence senior stakeholders.
• Nice-to-have: Demonstrated experience or vision for applying Agentic AI/LLM-driven methods to EDA challenges and prior direct collaboration with foundries and EDA vendors on advanced nodes.

Education Requirements

Minimum qualifications specified by the posting: Bachelor's degree in Science, Engineering, or a related field plus 6+ years of ASIC design/verification/validation/integration experience; OR Master's degree plus 5+ years; OR PhD plus 4+ years. Preferred: Master's in Electrical/Electronic Engineering, Computer Engineering, or Computer Science with 12+ years. Fields referenced: Electrical/Electronic Engineering, Computer Engineering, Computer Science, or related technical disciplines. No specific certifications were listed.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.