Staff/Senior Staff Engineer, Synthesis & Timing Constraints

Job Title

Staff/Senior Staff Engineer, Synthesis & Timing Constraints

Role Summary

Lead timing-constraint development and synthesis methodology for complex SoC designs within the ASIC/SoC Implementation team. Collaborate with Architecture, RTL Design, Physical Design, and STA groups to deliver high-quality implementations on advanced process nodes.

Experience Level

Senior - typically 10–15 years of experience in ASIC/SoC implementation.

Responsibilities

Accountable for timing constraints, synthesis flow quality, and design convergence across IP, subsystem, and chip levels.

• Define, develop, and maintain timing constraints (SDC) at IP, subsystem, and chip levels.
• Drive RTL synthesis and optimization using Synopsys Design Compiler and Fusion Compiler.
• Analyze and resolve timing, area, power, and implementation challenges to meet design targets.
• Collaborate with Architecture, RTL, Physical Design, and STA teams to ensure design convergence.
• Develop and enhance methodologies, flows, and automation to improve productivity and quality.
• Support timing closure activities and promote best practices for synthesis and constraint management.
• Debug and resolve synthesis- and timing-related issues during execution.
• Contribute to flow improvements for advanced-node ASIC/SoC development.

Requirements

Must-have:

• 10–15 years of experience in ASIC/SoC implementation.
• Expert knowledge of Synopsys Design Compiler and Fusion Compiler.
• Strong understanding of Static Timing Analysis (STA), timing closure, and SDC methodology.
• Hands-on scripting experience in Tcl and/or Python.
• Experience with advanced-node implementation flows.
• Strong analytical, problem-solving, and debugging skills.
• Ability to work effectively with global cross-functional teams.

Nice-to-have:

• Experience with low-power design methodologies and optimization techniques.
• Knowledge of Physical Design and signoff flows.
• Familiarity with hierarchical and full-chip implementation methodologies.
• Successful experience supporting complex SoC tapeouts.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering or Electrical Engineering.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.