Staff/Senior Staff Engineer - AMS Verification

Job Title

Staff/Senior Staff Engineer - AMS Verification

Role Summary

Lead verification of analog/mixed-signal (AMS) IPs and SoCs with emphasis on functionality, performance and power sign-off. Responsible for developing behavioral/RNM models, testbenches and verification plans and for driving closure through simulation, synthesis and silicon correlation.

The role requires close collaboration with Design, SoC, Validation, Synthesis and PD teams and ownership of block- and chip-level verification for mixed-signal subsystems.

Experience Level

Senior — 10–15 years of industry experience.

Responsibilities

Key responsibilities include planning and executing AMS verification for IPs and SoCs, developing models and test infrastructure, and driving cross-functional sign-off.

• Lead AMS verification efforts for mixed-signal IPs, subsystems and SoCs.
• Develop and validate behavioral/RNM models (Verilog-A/Verilog-AMS/Verilog-D) for performance and power analysis.
• Design and implement testbenches, self-checking tests and regression suites; use SV/UVM where applicable from an MS perspective.
• Perform simulation-based verification (Cadence/Synopsys/Mentor flows, SPICE simulators) and extract/present results for peer review.
• Verify block-level and chip-level functionality, performance and power; support silicon evaluation and correlate measurements to simulation.
• Collaborate with Design, SoC, Validation, Synthesis and PD teams to achieve design convergence.
• Drive verification closure and mentor or lead project teams in a multi-site environment.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Must-have: Proficiency in Verilog, SystemVerilog and/or Verilog-AMS; strong analog circuit knowledge and digital design/top-level integration experience.
• Proven experience in AMS verification on multiple SoCs or subsystems.
• Excellent simulation debugging and waveform analysis skills; ability to identify issues in schematics, models or RTL.
• Familiarity with AMS simulation environments and Cadence-based flows (Virtuoso, SPICE simulators).
• Proficient in Unix/shell scripting and basic Python; knowledge of Tcl/Perl/Skill is a plus.
• Basic knowledge of PMICs and DC–DC converters.
• Ability to lead projects and work collaboratively across distributed teams.
• Nice-to-have: UVM and assertion experience from a mixed-signal perspective; prior analog design experience; mentoring skills.

Education Requirements

Bachelor's or Master’s degree in Electrical and/or Computer Engineering.

About the Company

Company: Silicon Labs

Headquarters: Austin, Texas, USA

Silicon Labs is a leading innovator in low-power wireless connectivity, creating embedded technology that connects devices to improve lives. With a focus on advanced edge connectivity applications, the company provides device makers with cutting-edge solutions and support. Headquartered in Austin, Texas, Silicon Labs operates in over 16 countries, serving markets such as smart home, industrial IoT, and smart cities.