Staff RTL Design Engineer - PCIe

Job Title

Staff RTL Design Engineer - PCIe

Role Summary

Staff RTL Design Engineer responsible for micro‑architecture definition, RTL implementation, and integration of PCIe/CXL subsystems within Marvell's Data Centre Compute & Storage product group. The role works across architecture, verification, physical design and validation teams to deliver production silicon.

Experience Level

Senior (Staff-level). The posting references ~4+ years of relevant RTL design experience.

Responsibilities

Primary responsibilities include ownership of PCIe/CXL subsystem RTL and technical leadership within the design domain.

• Define and drive PCIe/CXL subsystem micro‑architecture and RTL implementation.
• Translate architecture requirements into robust RTL designs in collaboration with architecture teams.
• Work with design verification on test‑plan reviews, debug, and coverage closure.
• Partner with Physical Design and DFT teams to ensure PD‑friendly and DFT‑ready RTL.
• Support silicon bring‑up and post‑silicon debug with firmware and validation teams.
• Improve design quality, enforce coding best practices, and promote reuse across projects.
• Participate in design and milestone reviews and lead cross‑functional technical discussions.
• Mentor and provide technical guidance to junior designers.

Requirements

Key technical skills and domain experience required for successful performance in this role.

• Proven experience in end‑to‑end PCIe/CXL subsystem RTL design execution and sign‑off.
• Delivery of complex PCIe/CXL IP or subsystems from architecture through RTL closure.
• Hands‑on SystemVerilog / Verilog RTL development experience.
• Strong expertise in PCIe protocol architecture (link, transaction, PHY interaction).
• Deep understanding of CXL.io, CXL.cache, and CXL.mem architectures.
• Experience with ARM‑based SoC integration and AMBA protocols (AXI‑4, CHI, ACE).
• Design experience for high‑performance, low‑latency data paths, including ordering, coherency, and error handling.
• Solid grasp of clocking, resets, CDC/RDC, low‑power techniques, and performance optimization.
• Experience supporting lint, CDC/RDC, synthesis, and design sign‑off flows.
• Proficient at debugging functional and performance issues at subsystem and SoC levels.
• Familiarity with industry EDA tools (Synopsys, Cadence, Mentor/Siemens) and version control systems (GIT, SVN).
• Proficient in scripting (Tcl, Perl, Python) for automation and debug support.
• Role may require eligibility to access technology subject to U.S. export control laws; candidates may be subject to export license review prior to employment.
• Interview policy: use of AI tools during interviews is not permitted.

Education Requirements

Master's or Bachelor's degree in Electronics / Electrical Engineering is specified in the posting ("Master’s/Bachelor’s degree in Electronics/electrical Engineering with 4+ years of relevant experience").

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.